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Line 17... |
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// out = (v0 & l0) | (v1 & l1) | (v2 & l2) | ... | (v5 & l5)
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// out = (v0 & l0) | (v1 & l1) | (v2 & l2) | ... | (v5 & l5)
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module f3m_mux6(v0, v1, v2, v3, v4, v5, l0, l1, l2, l3, l4, l5, out);
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module f3m_mux6(v0, v1, v2, v3, v4, v5, l0, l1, l2, l3, l4, l5, out);
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input l0, l1, l2, l3, l4, l5;
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input l0, l1, l2, l3, l4, l5;
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input [`WIDTH:0] v0, v1, v2, v3, v4, v5;
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input [`WIDTH:0] v0, v1, v2, v3, v4, v5;
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output reg [`WIDTH:0] out;
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output [`WIDTH:0] out;
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always @ (l0,l1,l2,l3,l4,l5,v0,v1,v2,v3,v4,v5)
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genvar i;
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case ({l0,l1,l2,l3,l4,l5})
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generate
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6'b100000: out = v0;
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for(i=0;i<=`WIDTH;i=i+1)
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6'b010000: out = v1;
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begin : label
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6'b001000: out = v2;
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assign out[i] = (v0[i]&l0)|(v1[i]&l1)|(v2[i]&l2)|(v3[i]&l3)|(v4[i]&l4)|(v5[i]&l5);
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6'b000100: out = v3;
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end
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6'b000010: out = v4;
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endgenerate
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6'b000001: out = v5;
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default: out = 0;
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endcase
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endmodule
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endmodule
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// f3m_add: C = A + B, in field F_{3^M}
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// f3m_add: C = A + B, in field F_{3^M}
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module f3m_add(A, B, C);
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module f3m_add(A, B, C);
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input [`WIDTH : 0] A, B;
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input [`WIDTH : 0] A, B;
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