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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.basic_size.all;
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package basic_component is
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component parallel_find_top is
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GENERIC (N: NATURAL := N ; WIDTH :NATURAL := WIDTH);
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port ( a : in WORD_ARRAY;
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y : out STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0)
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);
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end component parallel_find_top;
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component mux_sel is
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GENERIC (level:INTEGER:=0; Cell_count:INTEGER:=8);
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port(
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left_op: in std_logic_vector(Cell_count-1 downto 0 );
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right_op: in std_logic_vector(Cell_count-1 downto 0 );
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o: out std_logic_vector(Cell_count-1 downto 0 )
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);
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end component mux_sel;
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component Ripple is
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GENERIC (cells : Natural:=6);
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port(
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left_op : IN std_logic_vector (cells -1 DOWNTO 0);
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right_op : IN std_logic_vector (cells -1 DOWNTO 0);
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choose_cur : out std_logic;
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found_cur : out std_logic;
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choose_sel : OUT std_logic_vector (cells -1 DOWNTO 0));
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end component Ripple;
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component Result is
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GENERIC (Cell_count : Natural:=6);
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port(
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i1: in std_logic_vector(Cell_count-1 downto 0);
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i2: in std_logic_vector(Cell_count-1 downto 0);
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choose_sel : In std_logic_vector(Cell_count-1 downto 0);
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o: out std_logic_vector(Cell_count-1 downto 0 ));
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end component Result;
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COMPONENT carry_cell_NOR is
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port(
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a: IN std_logic;
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b: IN std_logic;
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choose_prev : in std_logic;
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found_prev : in std_logic;
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choose_cur_bar : out std_logic;
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found_cur_bar : out std_logic);
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end COMPONENT carry_cell_NOR;
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COMPONENT carry_cell_NAND is
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port(
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a: IN std_logic;
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b: IN std_logic;
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choose_prev_bar : in std_logic;
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found_prev_bar : in std_logic;
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choose_cur : out std_logic;
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found_cur : out std_logic);
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end COMPONENT carry_cell_NAND;
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end package basic_component;
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package body basic_component is
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end package body;
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