-- <File header>
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-- <File header>
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-- Project
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-- Project
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-- pAVR (pipelined AVR) is an 8 bit RISC controller, compatible with Atmel's
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-- pAVR (pipelined AVR) is an 8 bit RISC controller, compatible with Atmel's
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-- AVR core, but about 3x faster in terms of both clock frequency and MIPS.
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-- AVR core, but about 3x faster in terms of both clock frequency and MIPS.
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-- The increase in speed comes from a relatively deep pipeline. The original
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-- The increase in speed comes from a relatively deep pipeline. The original
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-- AVR core has only two pipeline stages (fetch and execute), while pAVR has
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-- AVR core has only two pipeline stages (fetch and execute), while pAVR has
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-- 6 pipeline stages:
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-- 6 pipeline stages:
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-- 1. PM (read Program Memory)
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-- 1. PM (read Program Memory)
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-- 2. INSTR (load Instruction)
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-- 2. INSTR (load Instruction)
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-- 3. RFRD (decode Instruction and read Register File)
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-- 3. RFRD (decode Instruction and read Register File)
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-- 4. OPS (load Operands)
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-- 4. OPS (load Operands)
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-- 5. ALU (execute ALU opcode or access Unified Memory)
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-- 5. ALU (execute ALU opcode or access Unified Memory)
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-- 6. RFWR (write Register File)
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-- 6. RFWR (write Register File)
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-- Version
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-- Version
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-- 0.32
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-- 0.32
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-- Date
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-- Date
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-- 2002 August 07
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-- 2002 August 07
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-- Author
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-- Author
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-- Doru Cuturela, doruu@yahoo.com
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-- Doru Cuturela, doruu@yahoo.com
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-- License
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-- License
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-- This program is free software; you can redistribute it and/or modify
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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-- (at your option) any later version.
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-- This program is distributed in the hope that it will be useful,
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-- </File header>
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-- </File header>
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-- <File info>
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-- <File info>
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-- This file contains:
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-- This file contains:
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-- - Type conversion routines ofted used throughout the other source files in
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-- - Type conversion routines ofted used throughout the other source files in
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-- this project
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-- this project
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-- - Basic arithmetic functions
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-- - Basic arithmetic functions
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-- *** Multiplication is not yet defined! It will be defined here.
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-- *** Multiplication is not yet defined! It will be defined here.
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-- - Sign and zero-extend functions
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-- - Sign and zero-extend functions
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-- - Vector comparision function
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-- - Vector comparision function
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-- </File info>
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-- </File info>
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-- <File body>
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-- <File body>
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_signed.all;
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use ieee.std_logic_signed.all;
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package std_util is
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package std_util is
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function std_logic_vector_to_int(vec: std_logic_vector) return integer;
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function std_logic_vector_to_int(vec: std_logic_vector) return integer;
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function std_logic_vector_to_nat(vec: std_logic_vector) return natural;
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function std_logic_vector_to_nat(vec: std_logic_vector) return natural;
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function int_to_std_logic_vector(i, len: integer) return std_logic_vector;
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function int_to_std_logic_vector(i, len: integer) return std_logic_vector;
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function "+"(a: std_logic_vector; b: std_logic_vector) return std_logic_vector;
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function "+"(a: std_logic_vector; b: std_logic_vector) return std_logic_vector;
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function "+"(a: std_logic_vector; b: integer) return std_logic_vector;
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function "+"(a: std_logic_vector; b: integer) return std_logic_vector;
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function "-"(a: std_logic_vector; b: std_logic_vector) return std_logic_vector;
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function "-"(a: std_logic_vector; b: std_logic_vector) return std_logic_vector;
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function "-"(a: std_logic_vector; b: integer) return std_logic_vector;
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function "-"(a: std_logic_vector; b: integer) return std_logic_vector;
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function sign_extend(a: std_logic_vector; wxtd: natural) return std_logic_vector;
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function sign_extend(a: std_logic_vector; wxtd: natural) return std_logic_vector;
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function zero_extend(a: std_logic_vector; wxtd: natural) return std_logic_vector;
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function zero_extend(a: std_logic_vector; wxtd: natural) return std_logic_vector;
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function cmp_std_logic_vector(a: std_logic_vector; b: std_logic_vector) return std_logic;
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function cmp_std_logic_vector(a: std_logic_vector; b: std_logic_vector) return std_logic;
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end;
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end;
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package body std_util is
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package body std_util is
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function std_logic_vector_to_int(vec: std_logic_vector) return integer is
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function std_logic_vector_to_int(vec: std_logic_vector) return integer is
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variable i: integer;
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variable i: integer;
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begin
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begin
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i := conv_integer(vec);
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i := conv_integer(vec);
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return(i);
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return(i);
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end;
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end;
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function std_logic_vector_to_nat(vec: std_logic_vector) return natural is
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function std_logic_vector_to_nat(vec: std_logic_vector) return natural is
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variable tmp: std_logic_vector(vec'length downto 0);
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variable tmp: std_logic_vector(vec'length downto 0);
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variable n: natural;
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variable n: natural;
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begin
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begin
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assert (vec'length < 32)
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assert (vec'length < 32)
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report "Error: vector length > 31 in function `std_logic_vector_to_nat'."
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report "Error: vector length > 31 in function `std_logic_vector_to_nat'."
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severity failure;
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severity failure;
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tmp := '0' & vec;
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tmp := '0' & vec;
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n := conv_integer(tmp);
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n := conv_integer(tmp);
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return(n);
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return(n);
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end;
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end;
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function int_to_std_logic_vector(i, len: integer) return std_logic_vector is
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function int_to_std_logic_vector(i, len: integer) return std_logic_vector is
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variable r: std_logic_vector(len - 1 downto 0);
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variable r: std_logic_vector(len - 1 downto 0);
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variable r1: std_logic_vector(len downto 0);
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variable r1: std_logic_vector(len downto 0);
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begin
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begin
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r1 := conv_std_logic_vector(i, len + 1);
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r1 := conv_std_logic_vector(i, len + 1);
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r := r1(len - 1 downto 0);
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r := r1(len - 1 downto 0);
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return(r);
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return(r);
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end;
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end;
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function "+"(a: std_logic_vector; b: std_logic_vector) return std_logic_vector is
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function "+"(a: std_logic_vector; b: std_logic_vector) return std_logic_vector is
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begin
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begin
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return(signed(a) + signed(b));
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return(signed(a) + signed(b));
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end;
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end;
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function "+"(a: std_logic_vector; b: integer) return std_logic_vector is
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function "+"(a: std_logic_vector; b: integer) return std_logic_vector is
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begin
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begin
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return(signed(a) + b);
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return(signed(a) + b);
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end;
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end;
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function "-"(a: std_logic_vector; b: std_logic_vector) return std_logic_vector is
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function "-"(a: std_logic_vector; b: std_logic_vector) return std_logic_vector is
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begin
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begin
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return(signed(a) - signed(b));
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return(signed(a) - signed(b));
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end;
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end;
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function "-"(a: std_logic_vector; b: integer) return std_logic_vector is
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function "-"(a: std_logic_vector; b: integer) return std_logic_vector is
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begin
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begin
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return (signed(a) - b);
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return (signed(a) - b);
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end;
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end;
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function sign_extend(a: std_logic_vector; wxtd: natural) return std_logic_vector is
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function sign_extend(a: std_logic_vector; wxtd: natural) return std_logic_vector is
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variable r: std_logic_vector(wxtd - 1 downto 0);
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variable r: std_logic_vector(wxtd - 1 downto 0);
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begin
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begin
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assert (a'length <= wxtd)
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assert (a'length <= wxtd)
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report "Error: vector length > extended vector length in function `sign_extend'."
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report "Error: vector length > extended vector length in function `sign_extend'."
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severity failure;
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severity failure;
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for i in 0 to a'length-1 loop
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for i in 0 to a'length-1 loop
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r(i) := a(i);
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r(i) := a(i);
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end loop;
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end loop;
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for i in a'length to wxtd - 1 loop
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for i in a'length to wxtd - 1 loop
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r(i) := a(a'length - 1);
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r(i) := a(a'length - 1);
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end loop;
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end loop;
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return r;
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return r;
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end;
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end;
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function zero_extend(a: std_logic_vector; wxtd: natural) return std_logic_vector is
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function zero_extend(a: std_logic_vector; wxtd: natural) return std_logic_vector is
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variable r: std_logic_vector(wxtd - 1 downto 0);
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variable r: std_logic_vector(wxtd - 1 downto 0);
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begin
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begin
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assert (a'length <= wxtd)
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assert (a'length <= wxtd)
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report "Error: vector length > extended vector length in function `sign_extend'."
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report "Error: vector length > extended vector length in function `sign_extend'."
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severity failure;
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severity failure;
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for i in 0 to a'length-1 loop
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for i in 0 to a'length-1 loop
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r(i) := a(i);
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r(i) := a(i);
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end loop;
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end loop;
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for i in a'length to wxtd - 1 loop
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for i in a'length to wxtd - 1 loop
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r(i) := '0';
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r(i) := '0';
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end loop;
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end loop;
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return r;
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return r;
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end;
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end;
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function cmp_std_logic_vector(a: std_logic_vector; b: std_logic_vector) return std_logic is
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function cmp_std_logic_vector(a: std_logic_vector; b: std_logic_vector) return std_logic is
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variable r: std_logic;
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variable r: std_logic;
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begin
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begin
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assert (a'length = b'length)
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assert (a'length = b'length)
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report "Error: vectors don't have the same length in function `cmp_std_logic_vector'."
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report "Error: vectors don't have the same length in function `cmp_std_logic_vector'."
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severity failure;
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severity failure;
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r := '1';
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r := '1';
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for i in 0 to a'length - 1 loop
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for i in 0 to a'length - 1 loop
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if (a(i) /= b(i)) then
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if (a(i) /= b(i)) then
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r := '0';
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r := '0';
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end if;
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end if;
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end loop;
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end loop;
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return r;
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return r;
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end;
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end;
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end;
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end;
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-- </File body>
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-- </File body>
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