-- <File header>
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-- <File header>
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-- Project
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-- Project
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-- pAVR (pipelined AVR) is an 8 bit RISC controller, compatible with Atmel's
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-- pAVR (pipelined AVR) is an 8 bit RISC controller, compatible with Atmel's
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-- AVR core, but about 3x faster in terms of both clock frequency and MIPS.
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-- AVR core, but about 3x faster in terms of both clock frequency and MIPS.
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-- The increase in speed comes from a relatively deep pipeline. The original
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-- The increase in speed comes from a relatively deep pipeline. The original
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-- AVR core has only two pipeline stages (fetch and execute), while pAVR has
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-- AVR core has only two pipeline stages (fetch and execute), while pAVR has
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-- 6 pipeline stages:
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-- 6 pipeline stages:
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-- 1. PM (read Program Memory)
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-- 1. PM (read Program Memory)
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-- 2. INSTR (load Instruction)
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-- 2. INSTR (load Instruction)
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-- 3. RFRD (decode Instruction and read Register File)
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-- 3. RFRD (decode Instruction and read Register File)
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-- 4. OPS (load Operands)
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-- 4. OPS (load Operands)
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-- 5. ALU (execute ALU opcode or access Unified Memory)
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-- 5. ALU (execute ALU opcode or access Unified Memory)
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-- 6. RFWR (write Register File)
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-- 6. RFWR (write Register File)
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-- Version
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-- Version
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-- 0.32
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-- 0.32
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-- Date
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-- Date
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-- 2002 August 07
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-- 2002 August 07
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-- Author
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-- Author
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-- Doru Cuturela, doruu@yahoo.com
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-- Doru Cuturela, doruu@yahoo.com
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-- License
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-- License
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-- This program is free software; you can redistribute it and/or modify
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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-- (at your option) any later version.
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-- This program is distributed in the hope that it will be useful,
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-- </File header>
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-- </File header>
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-- <File info>
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-- <File info>
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-- Test pAVR's ALU.
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-- Test pAVR's ALU.
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-- Note that the ALU is an asynchronous device.
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-- Note that the ALU is an asynchronous device.
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-- Check ALU output and flags output for all ALU opcodes, one by one, for all of
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-- Check ALU output and flags output for all ALU opcodes, one by one, for all of
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-- these situations:
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-- these situations:
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-- - carry in = 0
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-- - carry in = 0
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-- - carry in = 1
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-- - carry in = 1
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-- - additions generate overflow
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-- - additions generate overflow
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-- - substractions generate overflow
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-- - substractions generate overflow
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-- There are 26 ALU opcodes to be checked for each situation.
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-- There are 26 ALU opcodes to be checked for each situation.
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-- </File info>
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-- </File info>
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-- <File body>
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-- <File body>
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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library work;
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library work;
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use work.std_util.all;
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use work.std_util.all;
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use work.pavr_util.all;
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use work.pavr_util.all;
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use work.pavr_constants.all;
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use work.pavr_constants.all;
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entity test_alu is
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entity test_alu is
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end;
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end;
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architecture test_alu_arch of test_alu is
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architecture test_alu_arch of test_alu is
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signal clk: std_logic;
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signal clk: std_logic;
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-- ALU inputs
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-- ALU inputs
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signal alu_op1: std_logic_vector(15 downto 0);
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signal alu_op1: std_logic_vector(15 downto 0);
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signal alu_op2: std_logic_vector(7 downto 0);
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signal alu_op2: std_logic_vector(7 downto 0);
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signal alu_opcode: std_logic_vector(pavr_alu_opcode_w - 1 downto 0);
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signal alu_opcode: std_logic_vector(pavr_alu_opcode_w - 1 downto 0);
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signal alu_flagsin: std_logic_vector(5 downto 0);
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signal alu_flagsin: std_logic_vector(5 downto 0);
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-- ALU outputs
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-- ALU outputs
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signal alu_out: std_logic_vector(15 downto 0);
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signal alu_out: std_logic_vector(15 downto 0);
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signal alu_flagsout: std_logic_vector(5 downto 0);
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signal alu_flagsout: std_logic_vector(5 downto 0);
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-- Declare the ALU.
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-- Declare the ALU.
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component pavr_alu
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component pavr_alu
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port(
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port(
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pavr_alu_op1: in std_logic_vector(15 downto 0);
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pavr_alu_op1: in std_logic_vector(15 downto 0);
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pavr_alu_op2: in std_logic_vector(7 downto 0);
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pavr_alu_op2: in std_logic_vector(7 downto 0);
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pavr_alu_out: out std_logic_vector(15 downto 0);
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pavr_alu_out: out std_logic_vector(15 downto 0);
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pavr_alu_opcode: in std_logic_vector(pavr_alu_opcode_w - 1 downto 0);
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pavr_alu_opcode: in std_logic_vector(pavr_alu_opcode_w - 1 downto 0);
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pavr_alu_flagsin: in std_logic_vector(5 downto 0);
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pavr_alu_flagsin: in std_logic_vector(5 downto 0);
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pavr_alu_flagsout: out std_logic_vector(5 downto 0)
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pavr_alu_flagsout: out std_logic_vector(5 downto 0)
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);
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);
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end component;
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end component;
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for all: pavr_alu use entity work.pavr_alu(pavr_alu_arch);
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for all: pavr_alu use entity work.pavr_alu(pavr_alu_arch);
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begin
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begin
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-- Instantiate the ALU.
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-- Instantiate the ALU.
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pavr_alu_instance1: pavr_alu
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pavr_alu_instance1: pavr_alu
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port map(
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port map(
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alu_op1,
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alu_op1,
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alu_op2,
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alu_op2,
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alu_out,
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alu_out,
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alu_opcode,
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alu_opcode,
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alu_flagsin,
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alu_flagsin,
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alu_flagsout
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alu_flagsout
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);
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);
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generate_clock:
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generate_clock:
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process
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process
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begin
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begin
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clk <= '1';
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clk <= '1';
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wait for 50 ns;
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wait for 50 ns;
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clk <= '0';
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clk <= '0';
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wait for 50 ns;
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wait for 50 ns;
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end process generate_clock;
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end process generate_clock;
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test_main:
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test_main:
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process
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process
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begin
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begin
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wait for 10 ns;
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wait for 10 ns;
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-- For each of the following test patterns, check each of:
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-- For each of the following test patterns, check each of:
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-- - input 1, input 2, flags input
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-- - input 1, input 2, flags input
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-- - output, flags output
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-- - output, flags output
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-- Test ALU output, for all ALU opcodes; carry in = 1.
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-- Test ALU output, for all ALU opcodes; carry in = 1.
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for i in 0 to 25 loop
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for i in 0 to 25 loop
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alu_op1 <= int_to_std_logic_vector(16#44F9#, alu_op1'length);
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alu_op1 <= int_to_std_logic_vector(16#44F9#, alu_op1'length);
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alu_op2 <= int_to_std_logic_vector(16#0A#, alu_op2'length);
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alu_op2 <= int_to_std_logic_vector(16#0A#, alu_op2'length);
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alu_opcode <= int_to_std_logic_vector(i, alu_opcode'length);
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alu_opcode <= int_to_std_logic_vector(i, alu_opcode'length);
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alu_flagsin <= "000001";
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alu_flagsin <= "000001";
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wait until clk'event and clk='1';
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wait until clk'event and clk='1';
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end loop;
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end loop;
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-- Test ALU output, for all ALU opcodes; carry in = 0.
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-- Test ALU output, for all ALU opcodes; carry in = 0.
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for i in 0 to 25 loop
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for i in 0 to 25 loop
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alu_op1 <= int_to_std_logic_vector(16#44F5#, alu_op1'length);
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alu_op1 <= int_to_std_logic_vector(16#44F5#, alu_op1'length);
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alu_op2 <= int_to_std_logic_vector(16#03#, alu_op2'length);
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alu_op2 <= int_to_std_logic_vector(16#03#, alu_op2'length);
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alu_opcode <= int_to_std_logic_vector(i, alu_opcode'length);
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alu_opcode <= int_to_std_logic_vector(i, alu_opcode'length);
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alu_flagsin <= "000000";
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alu_flagsin <= "000000";
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wait until clk'event and clk='1';
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wait until clk'event and clk='1';
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end loop;
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end loop;
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-- Test ALU output, for all ALU opcodes; carry in = 1. Additions (on both 8 bits and 16 bits) will generate carry out = 1.
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-- Test ALU output, for all ALU opcodes; carry in = 1. Additions (on both 8 bits and 16 bits) will generate carry out = 1.
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for i in 0 to 25 loop
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for i in 0 to 25 loop
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alu_op1 <= int_to_std_logic_vector(16#FFF8#, alu_op1'length);
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alu_op1 <= int_to_std_logic_vector(16#FFF8#, alu_op1'length);
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alu_op2 <= int_to_std_logic_vector(16#0C#, alu_op2'length);
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alu_op2 <= int_to_std_logic_vector(16#0C#, alu_op2'length);
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alu_opcode <= int_to_std_logic_vector(i, alu_opcode'length);
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alu_opcode <= int_to_std_logic_vector(i, alu_opcode'length);
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alu_flagsin <= "000001";
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alu_flagsin <= "000001";
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wait until clk'event and clk='1';
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wait until clk'event and clk='1';
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end loop;
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end loop;
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-- Test ALU output, for all ALU opcodes; carry in = 1. Substractions (on both 8 bits and 16 bits) will generate carry out = 1.
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-- Test ALU output, for all ALU opcodes; carry in = 1. Substractions (on both 8 bits and 16 bits) will generate carry out = 1.
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for i in 0 to 25 loop
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for i in 0 to 25 loop
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alu_op1 <= int_to_std_logic_vector(16#0005#, alu_op1'length);
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alu_op1 <= int_to_std_logic_vector(16#0005#, alu_op1'length);
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alu_op2 <= int_to_std_logic_vector(16#0C#, alu_op2'length);
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alu_op2 <= int_to_std_logic_vector(16#0C#, alu_op2'length);
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alu_opcode <= int_to_std_logic_vector(i, alu_opcode'length);
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alu_opcode <= int_to_std_logic_vector(i, alu_opcode'length);
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alu_flagsin <= "000001";
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alu_flagsin <= "000001";
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wait until clk'event and clk='1';
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wait until clk'event and clk='1';
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end loop;
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end loop;
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end process test_main;
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end process test_main;
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end;
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end;
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-- </File body>
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-- </File body>
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