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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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-- Company:
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-- Company:
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-- Engineer: Istvan Nagy, buenos@freemail.hu
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-- Engineer: Istvan Nagy, buenos@freemail.hu
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--
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--
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-- Create Date: 05/30/2010
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-- Create Date: 05/30/2010
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-- Modify date: 04/26/2011
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-- Modify date: 08/10/2012
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-- Design Name: pcie_mini
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-- Design Name: pcie_mini
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-- Module Name: xilinx_pcie2wb - Behavioral
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-- Module Name: xilinx_pcie2wb - Behavioral
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-- Version: 1.1
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-- Version: 1.2
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-- Project Name:
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-- Project Name:
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-- Target Devices: Xilinx Series-5/6/7 FPGAs
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-- Target Devices: Xilinx Series-5/6/7 FPGAs
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-- Tool versions: ISE-DS 12.1
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-- Tool versions: ISE-DS 12.1
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-- Description:
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-- Description:
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-- PCI-express endpoint block, transaction layer logic and back-end logic. The main
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-- PCI-express endpoint block, transaction layer logic and back-end logic. The main
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-- directory into the project's directory, and copy the generic section of the "pcie"
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-- directory into the project's directory, and copy the generic section of the "pcie"
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-- from the file: xilinx_pcie_1_1_ep_s6.vhd, into this file.
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-- from the file: xilinx_pcie_1_1_ep_s6.vhd, into this file.
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-- Synthesis: Set the "FSM Encoding Algorithm" to "user".
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-- Synthesis: Set the "FSM Encoding Algorithm" to "user".
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 0.01 - File Created
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-- Revision 1.0 - File Created by Istvan Nagy
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-- Revision 1.1 - some fixes by Istvan Nagy
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-- Revision 1.2 - interrupt fix by Stephen Battazzo
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--
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--
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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SIGNAL txtlp_data_5 : std_logic_vector(31 downto 0);
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SIGNAL txtlp_data_5 : std_logic_vector(31 downto 0);
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SIGNAL txtlp_data_6 : std_logic_vector(31 downto 0);
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SIGNAL txtlp_data_6 : std_logic_vector(31 downto 0);
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SIGNAL txtlp_data_7 : std_logic_vector(31 downto 0);
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SIGNAL txtlp_data_7 : std_logic_vector(31 downto 0);
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SIGNAL pcie_tlp_tx_complete : std_logic;
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SIGNAL pcie_tlp_tx_complete : std_logic;
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--this signal added by StBa, AAC Microtec
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SIGNAL irq_prohibit : std_logic;
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SIGNAL pcieirq_state : std_logic_vector(7 downto 0);
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SIGNAL pcieirq_state : std_logic_vector(7 downto 0);
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SIGNAL txtrn_counter : std_logic_vector(7 downto 0);
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SIGNAL txtrn_counter : std_logic_vector(7 downto 0);
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SIGNAL trn_rx_counter : std_logic_vector(7 downto 0);
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SIGNAL trn_rx_counter : std_logic_vector(7 downto 0);
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SIGNAL cfg_completer_id : std_logic_vector(15 downto 0);
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SIGNAL cfg_completer_id : std_logic_vector(15 downto 0);
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SIGNAL wb0_state : std_logic_vector(7 downto 0);
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SIGNAL wb0_state : std_logic_vector(7 downto 0);
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SLOT_CAP_ATT_BUTTON_PRESENT : boolean := FALSE;
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SLOT_CAP_ATT_BUTTON_PRESENT : boolean := FALSE;
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SLOT_CAP_ATT_INDICATOR_PRESENT : boolean := FALSE;
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SLOT_CAP_ATT_INDICATOR_PRESENT : boolean := FALSE;
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SLOT_CAP_POWER_INDICATOR_PRESENT : boolean := FALSE;
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SLOT_CAP_POWER_INDICATOR_PRESENT : boolean := FALSE;
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DEV_CAP_ROLE_BASED_ERROR : boolean := TRUE;
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DEV_CAP_ROLE_BASED_ERROR : boolean := TRUE;
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LINK_CAP_ASPM_SUPPORT : integer := 1;
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LINK_CAP_ASPM_SUPPORT : integer := 1;
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LINK_CAP_L0S_EXIT_LATENCY : integer := 7;
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--LINK_CAP_L0S_EXIT_LATENCY : integer := 7;
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LINK_CAP_L1_EXIT_LATENCY : integer := 7;
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--LINK_CAP_L1_EXIT_LATENCY : integer := 7;
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LL_ACK_TIMEOUT : bit_vector := x"0204";
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LL_ACK_TIMEOUT : bit_vector := x"0000";
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LL_ACK_TIMEOUT_EN : boolean := FALSE;
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LL_ACK_TIMEOUT_EN : boolean := FALSE;
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LL_REPLAY_TIMEOUT : bit_vector := x"0204";
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--LL_REPLAY_TIMEOUT : bit_vector := x"0204";
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LL_REPLAY_TIMEOUT : bit_vector := x"0000";
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LL_REPLAY_TIMEOUT_EN : boolean := FALSE;
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LL_REPLAY_TIMEOUT_EN : boolean := FALSE;
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MSI_CAP_MULTIMSGCAP : integer := 0;
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MSI_CAP_MULTIMSGCAP : integer := 0;
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MSI_CAP_MULTIMSG_EXTENSION : integer := 0;
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MSI_CAP_MULTIMSG_EXTENSION : integer := 0;
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LINK_STATUS_SLOT_CLOCK_CONFIG : boolean := FALSE;
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LINK_STATUS_SLOT_CLOCK_CONFIG : boolean := FALSE;
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PLM_AUTO_CONFIG : boolean := FALSE;
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PLM_AUTO_CONFIG : boolean := FALSE;
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PM_DATA7 : bit_vector := x"00";
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PM_DATA7 : bit_vector := x"00";
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PM_DATA_SCALE7 : bit_vector := x"0";
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PM_DATA_SCALE7 : bit_vector := x"0";
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PCIE_GENERIC : bit_vector := "000011101111";
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PCIE_GENERIC : bit_vector := "000011101111";
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GTP_SEL : integer := 0;
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GTP_SEL : integer := 0;
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CFG_VEN_ID : std_logic_vector(15 downto 0) := x"10EE";
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CFG_VEN_ID : std_logic_vector(15 downto 0) := x"10EE";
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CFG_DEV_ID : std_logic_vector(15 downto 0) := x"ABCD";
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CFG_DEV_ID : std_logic_vector(15 downto 0) := x"BADD";
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CFG_REV_ID : std_logic_vector(7 downto 0) := x"00";
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CFG_REV_ID : std_logic_vector(7 downto 0) := x"00";
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CFG_SUBSYS_VEN_ID : std_logic_vector(15 downto 0) := x"10EE";
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CFG_SUBSYS_VEN_ID : std_logic_vector(15 downto 0) := x"10EE";
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CFG_SUBSYS_ID : std_logic_vector(15 downto 0) := x"1234";
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CFG_SUBSYS_ID : std_logic_vector(15 downto 0) := x"1234";
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REF_CLK_FREQ : integer := 0
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REF_CLK_FREQ : integer := 0
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);
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);
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---- ------- SYNTHESIS ATTRIBUTES: --------------------------------------------------
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---- ------- SYNTHESIS ATTRIBUTES: --------------------------------------------------
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--attribute keep_hierarchy : string;
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--attribute keep_hierarchy : string;
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--attribute keep_hierarchy of xilinx_pcie2wb: entity is "yes";
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--attribute keep_hierarchy of xilinx_pcie2wb: entity is "yes";
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attribute keep : string;
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attribute keep of cfg_dstatus : signal is "true";
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attribute keep of tlp_state : signal is "true";
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-- --------ARCHITECTURE BODY BEGINS -----------------------------------------------
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-- --------ARCHITECTURE BODY BEGINS -----------------------------------------------
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begin
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begin
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--02h INTC
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--02h INTC
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--03h INTD
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--03h INTD
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cfg_interrupt_di <= "00000000"; --intA used
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cfg_interrupt_di <= "00000000"; --intA used
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--prohibit IRQ assert when TLP state machine not idle.
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-- if an IRQ is asserted between a read request and completion, it causes an error in the endpoint block.
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-- added by StBa, AAC Microtec, 2012
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irq_prohibit <= not tlpstm_isin_idle;
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process (pciewb_localreset_n, trn_clk, pcie_irq, pcieirq_state,
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process (pciewb_localreset_n, trn_clk, pcie_irq, pcieirq_state,
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cfg_interrupt_rdy_n)
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cfg_interrupt_rdy_n)
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begin
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begin
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if (pciewb_localreset_n='0') then
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if (pciewb_localreset_n='0') then
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pcieirq_state <= "00000000";
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pcieirq_state <= "00000000";
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Line 1391... |
if (trn_clk'event and trn_clk = '1') then
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if (trn_clk'event and trn_clk = '1') then
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case ( pcieirq_state ) is
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case ( pcieirq_state ) is
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--********** idle STATE **********
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--********** idle STATE **********
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when "00000000" => --state 0
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when "00000000" => --state 0
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if (pcie_irq = '1') then
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if (pcie_irq = '1' and irq_prohibit = '0') then
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pcieirq_state <= "00000001";
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pcieirq_state <= "00000001";
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cfg_interrupt_n <= '0'; --active
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cfg_interrupt_n <= '0'; --active
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else
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else
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cfg_interrupt_n <= '1'; --inactive
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cfg_interrupt_n <= '1'; --inactive
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end if;
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end if;
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Line 1410... |
cfg_interrupt_n <= '0'; --request INTA assertion
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cfg_interrupt_n <= '0'; --request INTA assertion
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end if;
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end if;
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--********** pcie_irq kept asserted STATE **********
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--********** pcie_irq kept asserted STATE **********
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when "00000010" => --state 2
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when "00000010" => --state 2
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if (pcie_irq = '0') then --pcie_irq gets deasserted
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if (pcie_irq = '0' and irq_prohibit='0') then --pcie_irq gets deasserted
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pcieirq_state <= "00000011";
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pcieirq_state <= "00000011";
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end if;
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end if;
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cfg_interrupt_n <= '1'; --inactive
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cfg_interrupt_n <= '1'; --inactive
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cfg_interrupt_assert_n_1 <= '1'; --0=assert, 1=deassert
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cfg_interrupt_assert_n_1 <= '1'; --0=assert, 1=deassert
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