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--
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--
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-- Create Date: 05/30/2010
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-- Create Date: 05/30/2010
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-- Modify date: 04/26/2011
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-- Modify date: 04/26/2011
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-- Design Name: pcie_mini
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-- Design Name: pcie_mini
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-- Module Name: xilinx_pcie2wb - Behavioral
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-- Module Name: xilinx_pcie2wb - Behavioral
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-- Version: 1.1
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-- Version: 1.2
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-- Project Name:
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-- Project Name:
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-- Target Devices: Xilinx Series-5/6/7 FPGAs
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-- Target Devices: Xilinx Series-5/6/7 FPGAs (This code is tested on Spartan-6 XC6SLX45T)
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-- Tool versions: ISE-DS 12.1
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-- Tool versions: ISE-DS 12.1
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-- Description:
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-- Description:
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-- PCI-express endpoint block, transaction layer logic and back-end logic. The main
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-- PCI-express endpoint block, transaction layer logic and back-end logic. The main
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-- purpose of this file is to make a useable back-end interface and handle flow control
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-- purpose of this file is to make a useable back-end interface and handle flow control
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-- for the xilinx auto-generated PCIe endpoint IP.
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-- for the xilinx auto-generated PCIe endpoint IP.
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| Line 38... |
Line 38... |
--
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--
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-- Dependencies: The CoreGenerator's configured PCIe core is included.
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-- Dependencies: The CoreGenerator's configured PCIe core is included.
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-- If we generate a new pcie endpoint, then copy the new files from the source
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-- If we generate a new pcie endpoint, then copy the new files from the source
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-- directory into the project's directory, and copy the generic section of the "pcie"
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-- directory into the project's directory, and copy the generic section of the "pcie"
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-- from the file: xilinx_pcie_1_1_ep_s6.vhd, into this file.
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-- from the file: xilinx_pcie_1_1_ep_s6.vhd, into this file.
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--
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-- Device Type Migration:
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-- This core should work on any Xilinx Series-5/6/7 FPGAs, but at now it runs on XC6SLX45T.
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-- For a new device (not an XC6SLX45T) we have to regenerate the Coregenerator cores,
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-- replace all BUFIO2/MGT/BUFG/BRAM (and other) to the chosen device's appropriate resources,
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-- in both the VHDL and the UCF sources. Also in the UCF the BUFIO2 and MGT placements
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-- will have to be re-specified with the appropriate resources/locations. The coregenerator
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-- will have to be set up to generate cores with the same parameters and ports as they are
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-- used here (to be useable as a drop-in replacement). Some resources are instantiated as
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-- part of the Coregen cores, so they will be chosen by Coregen appropriately, we just need
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-- to adjust their LOC placement constraints in the UCF file.
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--
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-- Coregenerator parameters:
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-- PCIe-EP: Name=pcie, Type=LegacyPCIe-EP, BAR0=mem/256MB, BAR1+=off, ROM=off, Max Payload=512Bytes,
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-- ASPM-L1=off, SlotCLK=off, IRQ=INTA, DeviceSpecInit=off, D1/D2=on, PME_from=D0,
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-- Set D0 power (4W), DSN=enabled, PCI_ConfSp=off, PCIe_Extended_ConfSp=off,
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-- no_scram =off, Xil_Refboard=None, RefClkFreq=125MHz, TranscLoc/Ch="leave default".
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-- Blockram: Name=blk_mem_gen_v4_1, Type=SimpleDpRAM, WriteEn=off, Algor=MinArea,
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-- WriteWidth=32, WriteDepth=512, Ena=AlwaysEnabled, ReadWidth=32, RegisterPorttB=off
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-- LoadInitFile=off, Fill=off, UseRSTB=off.
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--
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-- Synthesis: Set the "FSM Encoding Algorithm" to "user".
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-- Synthesis: Set the "FSM Encoding Algorithm" to "user".
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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Line 263... |
SIGNAL trn_tsrc_rdy_n_1 : std_logic;
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SIGNAL trn_tsrc_rdy_n_1 : std_logic;
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SIGNAL trn_tsof_n1 : std_logic;
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SIGNAL trn_tsof_n1 : std_logic;
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SIGNAL rcompl_bytecount_field : std_logic_vector(9 downto 0);
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SIGNAL rcompl_bytecount_field : std_logic_vector(9 downto 0);
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SIGNAL rxstm_readytoroll : std_logic;
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SIGNAL rxstm_readytoroll : std_logic;
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SIGNAL tlpstm_isin_idle : std_logic;
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SIGNAL tlpstm_isin_idle : std_logic;
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SIGNAL pcierx_detected : std_logic;
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SIGNAL pcierx_detect_ff_clear : std_logic;
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-- COMPONENT DECLARATIONS (introducing the IPs) --------------------------------
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-- COMPONENT DECLARATIONS (introducing the IPs) --------------------------------
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| Line 940... |
Line 962... |
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--fixed connections:
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--fixed connections:
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--trn_rnp_ok_ntrn_rnp_ok_n <= '0'; --ready to receive non-posted
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--trn_rnp_ok_ntrn_rnp_ok_n <= '0'; --ready to receive non-posted
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--not connected: trn_rerrfwd_n, trn_rsrc_dsc_n, trn_rbar_hit_n
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--not connected: trn_rerrfwd_n, trn_rsrc_dsc_n, trn_rbar_hit_n
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--RX detection flip-flop
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process (pciewb_localreset_n, trn_clk)
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begin
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if (pciewb_localreset_n='0') then
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pcierx_detected <= '0';
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else
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if (trn_clk'event and trn_clk = '1') then
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if (pcie_just_received_a_new_tlp ='1') then
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pcierx_detected <= '1';
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elsif (pcierx_detect_ff_clear ='1') then
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pcierx_detected <= '0';
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end if;
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end if;
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end if;
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end process;
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-- flow control: INTERFACE TO THE PCIE-EP: - ----
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-- flow control: INTERFACE TO THE PCIE-EP: - ----
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Line 990... |
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-- --- GLUE LOGIC BETWEEN THE PCIE CORE-IF AND THE WB INTERFACES -----------------------
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-- --- GLUE LOGIC BETWEEN THE PCIE CORE-IF AND THE WB INTERFACES -----------------------
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-- --- ALSO TLP PACKET PROCESSING.
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-- --- ALSO TLP PACKET PROCESSING.
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--Theory of operation:
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--Theory of operation:
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--RX: If we receive a TLP (pcie_just_received_a_new_tlp goes high for one clock cycle),
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--RX: If we receive a TLP (pcie_just_received_a_new_tlp goes high for one clock cycle),
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--then store it (pcie_received_tlp), decode it (to figure out if its read request,
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--then store it (pcie_received_tlp), decode it (to figure out if its read request,
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| Line 1009... |
Line 1047... |
--REQUESTER_ID------------------- tag------------ r lower_address
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--REQUESTER_ID------------------- tag------------ r lower_address
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--TLP-protocol statemachine:
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--TLP-protocol statemachine:
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process (pciewb_localreset_n, trn_clk, tlp_state,
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process (pciewb_localreset_n, trn_clk, tlp_state,
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pcie_just_received_a_new_tlp, tlp_datacount,
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pcierx_detected, tlp_datacount,
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bram_rxtlp_readdata, bram_txtlp_writeaddress, bram_rxtlp_readaddress,
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bram_rxtlp_readdata, bram_txtlp_writeaddress, bram_rxtlp_readaddress,
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tlp_state_copy, rxtlp_decodedaddress,
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tlp_state_copy, rxtlp_decodedaddress,
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rxtlp_header_dw1, rxtlp_header_dw2, rxtlp_header_dw3, rxtlp_header_dw4,
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rxtlp_header_dw1, rxtlp_header_dw2, rxtlp_header_dw3, rxtlp_header_dw4,
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bit10, rxtlp_firstdw_be, wb_transaction_complete, flag1, rxdw1_23_0, pcie_rxtlp_tag,
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bit10, rxtlp_firstdw_be, wb_transaction_complete, flag1, rxdw1_23_0, pcie_rxtlp_tag,
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tlp_payloadsize_dwords, pcie_bar0_wb_data_i_latched, cfg_completer_id,
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tlp_payloadsize_dwords, pcie_bar0_wb_data_i_latched, cfg_completer_id,
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| Line 1044... |
Line 1082... |
flag1 <= '0';
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flag1 <= '0';
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rxdw1_23_0 <= (others => '0');
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rxdw1_23_0 <= (others => '0');
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pcie_rxtlp_tag <= (others => '0');
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pcie_rxtlp_tag <= (others => '0');
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rcompl_bytecount_field <= (others => '0');
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rcompl_bytecount_field <= (others => '0');
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tlpstm_isin_idle <= '1';
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tlpstm_isin_idle <= '1';
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pcierx_detect_ff_clear <= '0';
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else
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else
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if (trn_clk'event and trn_clk = '1') then
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if (trn_clk'event and trn_clk = '1') then
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case ( tlp_state ) is
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case ( tlp_state ) is
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--********** IDLE STATE **********
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--********** IDLE STATE **********
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--also re-initialize signals...
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--also re-initialize signals...
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when "00000000" => --state 0
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when "00000000" => --state 0
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if (pcie_just_received_a_new_tlp='1') then
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if (pcierx_detected='1') then
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tlp_state <= "00000001"; --to tlp decoding state
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tlp_state <= "00000001"; --to tlp decoding state
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tlpstm_isin_idle <= '0';
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tlpstm_isin_idle <= '0';
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else
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else
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tlpstm_isin_idle <= '1';
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tlpstm_isin_idle <= '1';
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end if;
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end if;
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Line 1120... |
tlp_payloadsize_dwords <= (others => '0');
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tlp_payloadsize_dwords <= (others => '0');
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rxtlp_firstdw_be <= (others => '0');
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rxtlp_firstdw_be <= (others => '0');
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rxtlp_lastdw_be <= (others => '0');
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rxtlp_lastdw_be <= (others => '0');
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rxtlp_requesterid <= (others => '0');
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rxtlp_requesterid <= (others => '0');
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rcompl_bytecount_field <= (others => '0');
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rcompl_bytecount_field <= (others => '0');
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pcierx_detect_ff_clear <= '0';
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--********** TLP ARRIVED STATE **********
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--********** TLP ARRIVED STATE **********
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--read TLP out of EP, decode and decide,
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--read TLP out of EP, decode and decide,
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--latch address/sel/wr_data
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--latch address/sel/wr_data
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| Line 1093... |
Line 1133... |
when "00000001" => --state 1
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when "00000001" => --state 1
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--latch the header:
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--latch the header:
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bram_rxtlp_readaddress <= bram_rxtlp_readaddress +1;
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bram_rxtlp_readaddress <= bram_rxtlp_readaddress +1;
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if (bram_rxtlp_readaddress = "000000010") then
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if (bram_rxtlp_readaddress = "000000010") then
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rxtlp_header_dw1 <= bram_rxtlp_readdata;
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rxtlp_header_dw1 <= bram_rxtlp_readdata;
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pcierx_detect_ff_clear <= '1';
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elsif (bram_rxtlp_readaddress = "000000011") then
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elsif (bram_rxtlp_readaddress = "000000011") then
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rxtlp_header_dw2 <= bram_rxtlp_readdata;
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rxtlp_header_dw2 <= bram_rxtlp_readdata;
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elsif (bram_rxtlp_readaddress = "000000100") then
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elsif (bram_rxtlp_readaddress = "000000100") then
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rxtlp_header_dw3 <= bram_rxtlp_readdata;
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rxtlp_header_dw3 <= bram_rxtlp_readdata;
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pcierx_detect_ff_clear <= '0';
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elsif (bram_rxtlp_readaddress = "000000101") then
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elsif (bram_rxtlp_readaddress = "000000101") then
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rxtlp_header_dw4 <= bram_rxtlp_readdata;
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rxtlp_header_dw4 <= bram_rxtlp_readdata;
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end if;
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end if;
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--decode some parameters:
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--decode some parameters:
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tlp_payloadsize_dwords <= rxtlp_header_dw1(7 downto 0);
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tlp_payloadsize_dwords <= rxtlp_header_dw1(7 downto 0);
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| Line 1167... |
Line 1209... |
end if;
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end if;
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end if;
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end if;
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--* Write restart state *
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--* Write restart state *
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when "00010100" => --state 20
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when "00010100" => --state 20
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tlp_state <= "00000010";
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tlp_state <= "00000010";
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tlp_state_copy <= tlp_state;
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--********** READ STATE **********
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--********** READ STATE **********
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--initiate WB read, then go to completion state
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--initiate WB read, then go to completion state
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when "00000011" => --state 3
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when "00000011" => --state 3
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| Line 1199... |
Line 1242... |
end if;
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end if;
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--* read restart STATE *
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--* read restart STATE *
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when "00011110" => --state 30
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when "00011110" => --state 30
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tlp_state <= "00000011";
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tlp_state <= "00000011";
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bram_txtlp_we <= "0";
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bram_txtlp_we <= "0";
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tlp_state_copy <= tlp_state;
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--intermediate state before completion (to ensure data latch at address-4)
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--intermediate state before completion (to ensure data latch at address-4)
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when "01111110" => --state 126
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when "01111110" => --state 126
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tlp_state <= "00000100";
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tlp_state <= "00000100";
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tlp_state_copy <= tlp_state;
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bram_txtlp_writeaddress <= (OTHERS => '0');
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bram_txtlp_writeaddress <= (OTHERS => '0');
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--pre-write header-DW1:
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--pre-write header-DW1:
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bram_txtlp_writedata (31) <= flag1; --reserved
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bram_txtlp_writedata (31) <= flag1; --reserved
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bram_txtlp_writedata (30 downto 24) <= "1001010"; --type= rd completion
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bram_txtlp_writedata (30 downto 24) <= "1001010"; --type= rd completion
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bram_txtlp_writedata (23 downto 0) <= rxdw1_23_0; --various fields pcie_received_tlp (23 downto 0);
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bram_txtlp_writedata (23 downto 0) <= rxdw1_23_0; --various fields pcie_received_tlp (23 downto 0);
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