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-- If we generate a new pcie endpoint, then copy the new files from the source
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-- If we generate a new pcie endpoint, then copy the new files from the source
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-- directory into the project's directory, and copy the generic section of the "pcie"
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-- directory into the project's directory, and copy the generic section of the "pcie"
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-- from the file: xilinx_pcie_1_1_ep_s6.vhd, into this file.
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-- from the file: xilinx_pcie_1_1_ep_s6.vhd, into this file.
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--
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--
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-- Device Type Migration:
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-- Device Type Migration:
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-- This core should work on any Xilinx Series-5/6/7 FPGAs, but at now it runs on XC6SLX45T.
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-- This core was tested on Xilinx Spartan-6 FPGAs, specifically on the XC6SLX45T.
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-- For a new device (not an XC6SLX45T) we have to regenerate the Coregenerator cores,
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-- For a new device (not an XC6SLX45T) we have to regenerate the Coregenerator cores,
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-- replace all BUFIO2/MGT/BUFG/BRAM (and other) to the chosen device's appropriate resources,
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-- replace all BUFIO2/MGT/BUFG/BRAM (and other) to the chosen device's appropriate resources,
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-- in both the VHDL and the UCF sources. Also in the UCF the BUFIO2 and MGT placements
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-- in both the VHDL and the UCF sources. Also in the UCF the BUFIO2 and MGT placements
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-- will have to be re-specified with the appropriate resources/locations. The coregenerator
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-- will have to be re-specified with the appropriate resources/locations. The coregenerator
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-- will have to be set up to generate cores with the same parameters and ports as they are
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-- will have to be set up to generate cores with the same parameters and ports as they are
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-- used here (to be useable as a drop-in replacement). Some resources are instantiated as
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-- used here (to be useable as a drop-in replacement). Some resources are instantiated as
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-- part of the Coregen cores, so they will be chosen by Coregen appropriately, we just need
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-- part of the Coregen cores, so they will be chosen by Coregen appropriately, we just need
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-- to adjust their LOC placement constraints in the UCF file.
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-- to adjust their LOC placement constraints in the UCF file.
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-- Use on 7-series FPGAs:
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-- Xilinx Series-7 FPGAs have only 64-bit bus support on the PCIe port for x1/x2,
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-- and 28bit for x4/x8. Initial compatibility can be maintained with minimal modifications, by
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-- replacing the TX and RX block-ram buffers to assymetrically sized port buffers. 64bit on the PCIE-EP side, and 32-bit on the other side. Also the first entry has to be corrected to be at address zero or address-2, since now it is at address-1 which will get misaligned after a port-width conversion. Also the TRN-interfaces have to be modified to work with the AXI4 interface used by the series-7 PCIE-EP blocks.
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--
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--
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-- Coregenerator parameters:
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-- Coregenerator parameters:
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-- PCIe-EP: Name=pcie, Type=LegacyPCIe-EP, BAR0=mem/256MB, BAR1+=off, ROM=off, Max Payload=512Bytes,
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-- PCIe-EP: Name=pcie, Type=LegacyPCIe-EP, BAR0=mem/256MB, BAR1+=off, ROM=off, Max Payload=512Bytes,
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-- ASPM-L1=off, SlotCLK=off, IRQ=INTA, DeviceSpecInit=off, D1/D2=on, PME_from=D0,
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-- ASPM-L1=off, SlotCLK=off, IRQ=INTA, DeviceSpecInit=off, D1/D2=on, PME_from=D0,
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-- Set D0 power (4W), DSN=enabled, PCI_ConfSp=off, PCIe_Extended_ConfSp=off,
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-- Set D0 power (4W), DSN=enabled, PCI_ConfSp=off, PCIe_Extended_ConfSp=off,
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