| Line 1... |
Line 1... |
----------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------
|
-- Company:
|
-- Company:
|
-- Engineer: Istvan Nagy, buenos@freemail.hu
|
-- Engineer: Istvan Nagy, buenos@freemail.hu
|
--
|
--
|
-- Create Date: 05/30/2010
|
-- Create Date: 05/30/2010
|
-- Modify date: 04/26/2011
|
-- Modify date: 08/10/2012
|
-- Design Name: pcie_mini
|
-- Design Name: pcie_mini
|
-- Module Name: xilinx_pcie2wb - Behavioral
|
-- Module Name: xilinx_pcie2wb - Behavioral
|
-- Version: 1.2
|
-- Version: 1.2
|
-- Project Name:
|
-- Project Name:
|
-- Target Devices: Xilinx Series-5/6/7 FPGAs (This code is tested on Spartan-6 XC6SLX45T)
|
-- Target Devices: Xilinx Series-5/6/7 FPGAs
|
-- Tool versions: ISE-DS 12.1
|
-- Tool versions: ISE-DS 12.1
|
-- Description:
|
-- Description:
|
-- PCI-express endpoint block, transaction layer logic and back-end logic. The main
|
-- PCI-express endpoint block, transaction layer logic and back-end logic. The main
|
-- purpose of this file is to make a useable back-end interface and handle flow control
|
-- purpose of this file is to make a useable back-end interface and handle flow control
|
-- for the xilinx auto-generated PCIe endpoint IP.
|
-- for the xilinx auto-generated PCIe endpoint IP.
|
| Line 38... |
Line 38... |
--
|
--
|
-- Dependencies: The CoreGenerator's configured PCIe core is included.
|
-- Dependencies: The CoreGenerator's configured PCIe core is included.
|
-- If we generate a new pcie endpoint, then copy the new files from the source
|
-- If we generate a new pcie endpoint, then copy the new files from the source
|
-- directory into the project's directory, and copy the generic section of the "pcie"
|
-- directory into the project's directory, and copy the generic section of the "pcie"
|
-- from the file: xilinx_pcie_1_1_ep_s6.vhd, into this file.
|
-- from the file: xilinx_pcie_1_1_ep_s6.vhd, into this file.
|
--
|
|
-- Device Type Migration:
|
|
-- This core was tested on Xilinx Spartan-6 FPGAs, specifically on the XC6SLX45T.
|
|
-- For a new device (not an XC6SLX45T) we have to regenerate the Coregenerator cores,
|
|
-- replace all BUFIO2/MGT/BUFG/BRAM (and other) to the chosen device's appropriate resources,
|
|
-- in both the VHDL and the UCF sources. Also in the UCF the BUFIO2 and MGT placements
|
|
-- will have to be re-specified with the appropriate resources/locations. The coregenerator
|
|
-- will have to be set up to generate cores with the same parameters and ports as they are
|
|
-- used here (to be useable as a drop-in replacement). Some resources are instantiated as
|
|
-- part of the Coregen cores, so they will be chosen by Coregen appropriately, we just need
|
|
-- to adjust their LOC placement constraints in the UCF file.
|
|
-- Use on 7-series FPGAs:
|
|
-- Xilinx Series-7 FPGAs have only 64-bit bus support on the PCIe port for x1/x2,
|
|
-- and 28bit for x4/x8. Initial compatibility can be maintained with minimal modifications, by
|
|
-- replacing the TX and RX block-ram buffers to assymetrically sized port buffers. 64bit on the PCIE-EP side, and 32-bit on the other side. Also the first entry has to be corrected to be at address zero or address-2, since now it is at address-1 which will get misaligned after a port-width conversion. Also the TRN-interfaces have to be modified to work with the AXI4 interface used by the series-7 PCIE-EP blocks.
|
|
|
|
--
|
|
-- Coregenerator parameters:
|
|
-- PCIe-EP: Name=pcie, Type=LegacyPCIe-EP, BAR0=mem/256MB, BAR1+=off, ROM=off, Max Payload=512Bytes,
|
|
-- ASPM-L1=off, SlotCLK=off, IRQ=INTA, DeviceSpecInit=off, D1/D2=on, PME_from=D0,
|
|
-- Set D0 power (4W), DSN=enabled, PCI_ConfSp=off, PCIe_Extended_ConfSp=off,
|
|
-- no_scram =off, Xil_Refboard=None, RefClkFreq=125MHz, TranscLoc/Ch="leave default".
|
|
-- Blockram: Name=blk_mem_gen_v4_1, Type=SimpleDpRAM, WriteEn=off, Algor=MinArea,
|
|
-- WriteWidth=32, WriteDepth=512, Ena=AlwaysEnabled, ReadWidth=32, RegisterPorttB=off
|
|
-- LoadInitFile=off, Fill=off, UseRSTB=off.
|
|
--
|
|
-- Synthesis: Set the "FSM Encoding Algorithm" to "user".
|
-- Synthesis: Set the "FSM Encoding Algorithm" to "user".
|
--
|
--
|
-- Revision:
|
-- Revision:
|
-- Revision 0.01 - File Created
|
-- Revision 1.0 - File Created by Istvan Nagy
|
|
-- Revision 1.1 - some fixes by Istvan Nagy
|
|
-- Revision 1.2 - interrupt fix by Stephen Battazzo
|
--
|
--
|
----------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------
|
|
|
library IEEE;
|
library IEEE;
|
use IEEE.STD_LOGIC_1164.ALL;
|
use IEEE.STD_LOGIC_1164.ALL;
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
|
|
| Line 232... |
Line 208... |
SIGNAL txtlp_data_5 : std_logic_vector(31 downto 0);
|
SIGNAL txtlp_data_5 : std_logic_vector(31 downto 0);
|
SIGNAL txtlp_data_6 : std_logic_vector(31 downto 0);
|
SIGNAL txtlp_data_6 : std_logic_vector(31 downto 0);
|
SIGNAL txtlp_data_7 : std_logic_vector(31 downto 0);
|
SIGNAL txtlp_data_7 : std_logic_vector(31 downto 0);
|
SIGNAL pcie_tlp_tx_complete : std_logic;
|
SIGNAL pcie_tlp_tx_complete : std_logic;
|
|
|
|
--this signal added by StBa, AAC Microtec
|
|
SIGNAL irq_prohibit : std_logic;
|
|
|
SIGNAL pcieirq_state : std_logic_vector(7 downto 0);
|
SIGNAL pcieirq_state : std_logic_vector(7 downto 0);
|
SIGNAL txtrn_counter : std_logic_vector(7 downto 0);
|
SIGNAL txtrn_counter : std_logic_vector(7 downto 0);
|
SIGNAL trn_rx_counter : std_logic_vector(7 downto 0);
|
SIGNAL trn_rx_counter : std_logic_vector(7 downto 0);
|
SIGNAL cfg_completer_id : std_logic_vector(15 downto 0);
|
SIGNAL cfg_completer_id : std_logic_vector(15 downto 0);
|
SIGNAL wb0_state : std_logic_vector(7 downto 0);
|
SIGNAL wb0_state : std_logic_vector(7 downto 0);
|
| Line 268... |
Line 247... |
SIGNAL trn_tsrc_rdy_n_1 : std_logic;
|
SIGNAL trn_tsrc_rdy_n_1 : std_logic;
|
SIGNAL trn_tsof_n1 : std_logic;
|
SIGNAL trn_tsof_n1 : std_logic;
|
SIGNAL rcompl_bytecount_field : std_logic_vector(9 downto 0);
|
SIGNAL rcompl_bytecount_field : std_logic_vector(9 downto 0);
|
SIGNAL rxstm_readytoroll : std_logic;
|
SIGNAL rxstm_readytoroll : std_logic;
|
SIGNAL tlpstm_isin_idle : std_logic;
|
SIGNAL tlpstm_isin_idle : std_logic;
|
SIGNAL pcierx_detected : std_logic;
|
|
SIGNAL pcierx_detect_ff_clear : std_logic;
|
|
|
|
|
|
|
|
|
|
-- COMPONENT DECLARATIONS (introducing the IPs) --------------------------------
|
-- COMPONENT DECLARATIONS (introducing the IPs) --------------------------------
|
| Line 325... |
Line 303... |
SLOT_CAP_ATT_BUTTON_PRESENT : boolean := FALSE;
|
SLOT_CAP_ATT_BUTTON_PRESENT : boolean := FALSE;
|
SLOT_CAP_ATT_INDICATOR_PRESENT : boolean := FALSE;
|
SLOT_CAP_ATT_INDICATOR_PRESENT : boolean := FALSE;
|
SLOT_CAP_POWER_INDICATOR_PRESENT : boolean := FALSE;
|
SLOT_CAP_POWER_INDICATOR_PRESENT : boolean := FALSE;
|
DEV_CAP_ROLE_BASED_ERROR : boolean := TRUE;
|
DEV_CAP_ROLE_BASED_ERROR : boolean := TRUE;
|
LINK_CAP_ASPM_SUPPORT : integer := 1;
|
LINK_CAP_ASPM_SUPPORT : integer := 1;
|
LINK_CAP_L0S_EXIT_LATENCY : integer := 7;
|
--LINK_CAP_L0S_EXIT_LATENCY : integer := 7;
|
LINK_CAP_L1_EXIT_LATENCY : integer := 7;
|
--LINK_CAP_L1_EXIT_LATENCY : integer := 7;
|
LL_ACK_TIMEOUT : bit_vector := x"0204";
|
LL_ACK_TIMEOUT : bit_vector := x"0000";
|
LL_ACK_TIMEOUT_EN : boolean := FALSE;
|
LL_ACK_TIMEOUT_EN : boolean := FALSE;
|
LL_REPLAY_TIMEOUT : bit_vector := x"0204";
|
--LL_REPLAY_TIMEOUT : bit_vector := x"0204";
|
|
LL_REPLAY_TIMEOUT : bit_vector := x"0000";
|
LL_REPLAY_TIMEOUT_EN : boolean := FALSE;
|
LL_REPLAY_TIMEOUT_EN : boolean := FALSE;
|
MSI_CAP_MULTIMSGCAP : integer := 0;
|
MSI_CAP_MULTIMSGCAP : integer := 0;
|
MSI_CAP_MULTIMSG_EXTENSION : integer := 0;
|
MSI_CAP_MULTIMSG_EXTENSION : integer := 0;
|
LINK_STATUS_SLOT_CLOCK_CONFIG : boolean := FALSE;
|
LINK_STATUS_SLOT_CLOCK_CONFIG : boolean := FALSE;
|
PLM_AUTO_CONFIG : boolean := FALSE;
|
PLM_AUTO_CONFIG : boolean := FALSE;
|
| Line 364... |
Line 343... |
PM_DATA7 : bit_vector := x"00";
|
PM_DATA7 : bit_vector := x"00";
|
PM_DATA_SCALE7 : bit_vector := x"0";
|
PM_DATA_SCALE7 : bit_vector := x"0";
|
PCIE_GENERIC : bit_vector := "000011101111";
|
PCIE_GENERIC : bit_vector := "000011101111";
|
GTP_SEL : integer := 0;
|
GTP_SEL : integer := 0;
|
CFG_VEN_ID : std_logic_vector(15 downto 0) := x"10EE";
|
CFG_VEN_ID : std_logic_vector(15 downto 0) := x"10EE";
|
CFG_DEV_ID : std_logic_vector(15 downto 0) := x"ABCD";
|
CFG_DEV_ID : std_logic_vector(15 downto 0) := x"BADD";
|
CFG_REV_ID : std_logic_vector(7 downto 0) := x"00";
|
CFG_REV_ID : std_logic_vector(7 downto 0) := x"00";
|
CFG_SUBSYS_VEN_ID : std_logic_vector(15 downto 0) := x"10EE";
|
CFG_SUBSYS_VEN_ID : std_logic_vector(15 downto 0) := x"10EE";
|
CFG_SUBSYS_ID : std_logic_vector(15 downto 0) := x"1234";
|
CFG_SUBSYS_ID : std_logic_vector(15 downto 0) := x"1234";
|
REF_CLK_FREQ : integer := 0
|
REF_CLK_FREQ : integer := 0
|
);
|
);
|
| Line 475... |
Line 454... |
|
|
|
|
---- ------- SYNTHESIS ATTRIBUTES: --------------------------------------------------
|
---- ------- SYNTHESIS ATTRIBUTES: --------------------------------------------------
|
--attribute keep_hierarchy : string;
|
--attribute keep_hierarchy : string;
|
--attribute keep_hierarchy of xilinx_pcie2wb: entity is "yes";
|
--attribute keep_hierarchy of xilinx_pcie2wb: entity is "yes";
|
|
attribute keep : string;
|
|
attribute keep of cfg_dstatus : signal is "true";
|
|
attribute keep of tlp_state : signal is "true";
|
|
|
|
|
-- --------ARCHITECTURE BODY BEGINS -----------------------------------------------
|
-- --------ARCHITECTURE BODY BEGINS -----------------------------------------------
|
begin
|
begin
|
|
|
| Line 967... |
Line 948... |
|
|
--fixed connections:
|
--fixed connections:
|
--trn_rnp_ok_ntrn_rnp_ok_n <= '0'; --ready to receive non-posted
|
--trn_rnp_ok_ntrn_rnp_ok_n <= '0'; --ready to receive non-posted
|
--not connected: trn_rerrfwd_n, trn_rsrc_dsc_n, trn_rbar_hit_n
|
--not connected: trn_rerrfwd_n, trn_rsrc_dsc_n, trn_rbar_hit_n
|
|
|
--RX detection flip-flop
|
|
process (pciewb_localreset_n, trn_clk)
|
|
begin
|
|
if (pciewb_localreset_n='0') then
|
|
pcierx_detected <= '0';
|
|
else
|
|
if (trn_clk'event and trn_clk = '1') then
|
|
if (pcie_just_received_a_new_tlp ='1') then
|
|
pcierx_detected <= '1';
|
|
elsif (pcierx_detect_ff_clear ='1') then
|
|
pcierx_detected <= '0';
|
|
end if;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
|
|
|
|
|
|
-- flow control: INTERFACE TO THE PCIE-EP: - ----
|
-- flow control: INTERFACE TO THE PCIE-EP: - ----
|
| Line 995... |
Line 961... |
|
|
|
|
|
|
|
|
|
|
|
|
-- --- GLUE LOGIC BETWEEN THE PCIE CORE-IF AND THE WB INTERFACES -----------------------
|
-- --- GLUE LOGIC BETWEEN THE PCIE CORE-IF AND THE WB INTERFACES -----------------------
|
-- --- ALSO TLP PACKET PROCESSING.
|
-- --- ALSO TLP PACKET PROCESSING.
|
--Theory of operation:
|
--Theory of operation:
|
--RX: If we receive a TLP (pcie_just_received_a_new_tlp goes high for one clock cycle),
|
--RX: If we receive a TLP (pcie_just_received_a_new_tlp goes high for one clock cycle),
|
--then store it (pcie_received_tlp), decode it (to figure out if its read request,
|
--then store it (pcie_received_tlp), decode it (to figure out if its read request,
|
| Line 1052... |
Line 1017... |
--REQUESTER_ID------------------- tag------------ r lower_address
|
--REQUESTER_ID------------------- tag------------ r lower_address
|
|
|
|
|
--TLP-protocol statemachine:
|
--TLP-protocol statemachine:
|
process (pciewb_localreset_n, trn_clk, tlp_state,
|
process (pciewb_localreset_n, trn_clk, tlp_state,
|
pcierx_detected, tlp_datacount,
|
pcie_just_received_a_new_tlp, tlp_datacount,
|
bram_rxtlp_readdata, bram_txtlp_writeaddress, bram_rxtlp_readaddress,
|
bram_rxtlp_readdata, bram_txtlp_writeaddress, bram_rxtlp_readaddress,
|
tlp_state_copy, rxtlp_decodedaddress,
|
tlp_state_copy, rxtlp_decodedaddress,
|
rxtlp_header_dw1, rxtlp_header_dw2, rxtlp_header_dw3, rxtlp_header_dw4,
|
rxtlp_header_dw1, rxtlp_header_dw2, rxtlp_header_dw3, rxtlp_header_dw4,
|
bit10, rxtlp_firstdw_be, wb_transaction_complete, flag1, rxdw1_23_0, pcie_rxtlp_tag,
|
bit10, rxtlp_firstdw_be, wb_transaction_complete, flag1, rxdw1_23_0, pcie_rxtlp_tag,
|
tlp_payloadsize_dwords, pcie_bar0_wb_data_i_latched, cfg_completer_id,
|
tlp_payloadsize_dwords, pcie_bar0_wb_data_i_latched, cfg_completer_id,
|
| Line 1087... |
Line 1052... |
flag1 <= '0';
|
flag1 <= '0';
|
rxdw1_23_0 <= (others => '0');
|
rxdw1_23_0 <= (others => '0');
|
pcie_rxtlp_tag <= (others => '0');
|
pcie_rxtlp_tag <= (others => '0');
|
rcompl_bytecount_field <= (others => '0');
|
rcompl_bytecount_field <= (others => '0');
|
tlpstm_isin_idle <= '1';
|
tlpstm_isin_idle <= '1';
|
pcierx_detect_ff_clear <= '0';
|
|
else
|
else
|
if (trn_clk'event and trn_clk = '1') then
|
if (trn_clk'event and trn_clk = '1') then
|
case ( tlp_state ) is
|
case ( tlp_state ) is
|
|
|
--********** IDLE STATE **********
|
--********** IDLE STATE **********
|
--also re-initialize signals...
|
--also re-initialize signals...
|
when "00000000" => --state 0
|
when "00000000" => --state 0
|
if (pcierx_detected='1') then
|
if (pcie_just_received_a_new_tlp='1') then
|
tlp_state <= "00000001"; --to tlp decoding state
|
tlp_state <= "00000001"; --to tlp decoding state
|
tlpstm_isin_idle <= '0';
|
tlpstm_isin_idle <= '0';
|
else
|
else
|
tlpstm_isin_idle <= '1';
|
tlpstm_isin_idle <= '1';
|
end if;
|
end if;
|
| Line 1125... |
Line 1089... |
tlp_payloadsize_dwords <= (others => '0');
|
tlp_payloadsize_dwords <= (others => '0');
|
rxtlp_firstdw_be <= (others => '0');
|
rxtlp_firstdw_be <= (others => '0');
|
rxtlp_lastdw_be <= (others => '0');
|
rxtlp_lastdw_be <= (others => '0');
|
rxtlp_requesterid <= (others => '0');
|
rxtlp_requesterid <= (others => '0');
|
rcompl_bytecount_field <= (others => '0');
|
rcompl_bytecount_field <= (others => '0');
|
pcierx_detect_ff_clear <= '0';
|
|
|
|
|
|
--********** TLP ARRIVED STATE **********
|
--********** TLP ARRIVED STATE **********
|
--read TLP out of EP, decode and decide,
|
--read TLP out of EP, decode and decide,
|
--latch address/sel/wr_data
|
--latch address/sel/wr_data
|
| Line 1138... |
Line 1101... |
when "00000001" => --state 1
|
when "00000001" => --state 1
|
--latch the header:
|
--latch the header:
|
bram_rxtlp_readaddress <= bram_rxtlp_readaddress +1;
|
bram_rxtlp_readaddress <= bram_rxtlp_readaddress +1;
|
if (bram_rxtlp_readaddress = "000000010") then
|
if (bram_rxtlp_readaddress = "000000010") then
|
rxtlp_header_dw1 <= bram_rxtlp_readdata;
|
rxtlp_header_dw1 <= bram_rxtlp_readdata;
|
pcierx_detect_ff_clear <= '1';
|
|
elsif (bram_rxtlp_readaddress = "000000011") then
|
elsif (bram_rxtlp_readaddress = "000000011") then
|
rxtlp_header_dw2 <= bram_rxtlp_readdata;
|
rxtlp_header_dw2 <= bram_rxtlp_readdata;
|
elsif (bram_rxtlp_readaddress = "000000100") then
|
elsif (bram_rxtlp_readaddress = "000000100") then
|
rxtlp_header_dw3 <= bram_rxtlp_readdata;
|
rxtlp_header_dw3 <= bram_rxtlp_readdata;
|
pcierx_detect_ff_clear <= '0';
|
|
elsif (bram_rxtlp_readaddress = "000000101") then
|
elsif (bram_rxtlp_readaddress = "000000101") then
|
rxtlp_header_dw4 <= bram_rxtlp_readdata;
|
rxtlp_header_dw4 <= bram_rxtlp_readdata;
|
end if;
|
end if;
|
--decode some parameters:
|
--decode some parameters:
|
tlp_payloadsize_dwords <= rxtlp_header_dw1(7 downto 0);
|
tlp_payloadsize_dwords <= rxtlp_header_dw1(7 downto 0);
|
| Line 1214... |
Line 1175... |
end if;
|
end if;
|
end if;
|
end if;
|
--* Write restart state *
|
--* Write restart state *
|
when "00010100" => --state 20
|
when "00010100" => --state 20
|
tlp_state <= "00000010";
|
tlp_state <= "00000010";
|
tlp_state_copy <= tlp_state;
|
|
|
|
|
|
--********** READ STATE **********
|
--********** READ STATE **********
|
--initiate WB read, then go to completion state
|
--initiate WB read, then go to completion state
|
when "00000011" => --state 3
|
when "00000011" => --state 3
|
| Line 1247... |
Line 1207... |
end if;
|
end if;
|
--* read restart STATE *
|
--* read restart STATE *
|
when "00011110" => --state 30
|
when "00011110" => --state 30
|
tlp_state <= "00000011";
|
tlp_state <= "00000011";
|
bram_txtlp_we <= "0";
|
bram_txtlp_we <= "0";
|
tlp_state_copy <= tlp_state;
|
|
--intermediate state before completion (to ensure data latch at address-4)
|
--intermediate state before completion (to ensure data latch at address-4)
|
when "01111110" => --state 126
|
when "01111110" => --state 126
|
tlp_state <= "00000100";
|
tlp_state <= "00000100";
|
tlp_state_copy <= tlp_state;
|
|
bram_txtlp_writeaddress <= (OTHERS => '0');
|
bram_txtlp_writeaddress <= (OTHERS => '0');
|
--pre-write header-DW1:
|
--pre-write header-DW1:
|
bram_txtlp_writedata (31) <= flag1; --reserved
|
bram_txtlp_writedata (31) <= flag1; --reserved
|
bram_txtlp_writedata (30 downto 24) <= "1001010"; --type= rd completion
|
bram_txtlp_writedata (30 downto 24) <= "1001010"; --type= rd completion
|
bram_txtlp_writedata (23 downto 0) <= rxdw1_23_0; --various fields pcie_received_tlp (23 downto 0);
|
bram_txtlp_writedata (23 downto 0) <= rxdw1_23_0; --various fields pcie_received_tlp (23 downto 0);
|
| Line 1415... |
Line 1373... |
--02h INTC
|
--02h INTC
|
--03h INTD
|
--03h INTD
|
|
|
cfg_interrupt_di <= "00000000"; --intA used
|
cfg_interrupt_di <= "00000000"; --intA used
|
|
|
|
--prohibit IRQ assert when TLP state machine not idle.
|
|
-- if an IRQ is asserted between a read request and completion, it causes an error in the endpoint block.
|
|
-- added by StBa, AAC Microtec, 2012
|
|
irq_prohibit <= not tlpstm_isin_idle;
|
|
|
process (pciewb_localreset_n, trn_clk, pcie_irq, pcieirq_state,
|
process (pciewb_localreset_n, trn_clk, pcie_irq, pcieirq_state,
|
cfg_interrupt_rdy_n)
|
cfg_interrupt_rdy_n)
|
begin
|
begin
|
if (pciewb_localreset_n='0') then
|
if (pciewb_localreset_n='0') then
|
pcieirq_state <= "00000000";
|
pcieirq_state <= "00000000";
|
| Line 1428... |
Line 1391... |
if (trn_clk'event and trn_clk = '1') then
|
if (trn_clk'event and trn_clk = '1') then
|
case ( pcieirq_state ) is
|
case ( pcieirq_state ) is
|
|
|
--********** idle STATE **********
|
--********** idle STATE **********
|
when "00000000" => --state 0
|
when "00000000" => --state 0
|
if (pcie_irq = '1') then
|
if (pcie_irq = '1' and irq_prohibit = '0') then
|
pcieirq_state <= "00000001";
|
pcieirq_state <= "00000001";
|
cfg_interrupt_n <= '0'; --active
|
cfg_interrupt_n <= '0'; --active
|
else
|
else
|
cfg_interrupt_n <= '1'; --inactive
|
cfg_interrupt_n <= '1'; --inactive
|
end if;
|
end if;
|
| Line 1447... |
Line 1410... |
cfg_interrupt_n <= '0'; --request INTA assertion
|
cfg_interrupt_n <= '0'; --request INTA assertion
|
end if;
|
end if;
|
|
|
--********** pcie_irq kept asserted STATE **********
|
--********** pcie_irq kept asserted STATE **********
|
when "00000010" => --state 2
|
when "00000010" => --state 2
|
if (pcie_irq = '0') then --pcie_irq gets deasserted
|
if (pcie_irq = '0' and irq_prohibit='0') then --pcie_irq gets deasserted
|
pcieirq_state <= "00000011";
|
pcieirq_state <= "00000011";
|
end if;
|
end if;
|
cfg_interrupt_n <= '1'; --inactive
|
cfg_interrupt_n <= '1'; --inactive
|
cfg_interrupt_assert_n_1 <= '1'; --0=assert, 1=deassert
|
cfg_interrupt_assert_n_1 <= '1'; --0=assert, 1=deassert
|
|
|
