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--
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--
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-- Create Date: 05/30/2010
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-- Create Date: 05/30/2010
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-- Modify date: 08/10/2012
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-- Modify date: 08/10/2012
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-- Design Name: pcie_mini
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-- Design Name: pcie_mini
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-- Module Name: xilinx_pcie2wb - Behavioral
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-- Module Name: xilinx_pcie2wb - Behavioral
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-- Version: 1.2
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-- Version: 1.4
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-- Project Name:
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-- Project Name:
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-- Target Devices: Xilinx Series-5/6/7 FPGAs
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-- Target Devices: Xilinx Series-5/6/7 FPGAs
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-- Tool versions: ISE-DS 12.1
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-- Tool versions: ISE-DS 12.1
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-- Description:
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-- Description:
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-- PCI-express endpoint block, transaction layer logic and back-end logic. The main
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-- PCI-express endpoint block, transaction layer logic and back-end logic. The main
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| Line 44... |
Line 44... |
--
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--
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-- Revision:
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-- Revision:
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-- Revision 1.0 - File Created by Istvan Nagy
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-- Revision 1.0 - File Created by Istvan Nagy
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-- Revision 1.1 - some fixes by Istvan Nagy
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-- Revision 1.1 - some fixes by Istvan Nagy
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-- Revision 1.2 - interrupt fix by Stephen Battazzo
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-- Revision 1.2 - interrupt fix by Stephen Battazzo
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-- Revision 1.3 - 64-bit read fix, support for unaligned 32-bit read, and custom BAR0 address space size by Scott Cogan, FRIB
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-- Revision 1.4 - Compatibility for MSI and Legacy interrupts by Scott Cogan, FRIB
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--
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--
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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| Line 60... |
Line 62... |
use UNISIM.VComponents.all;
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use UNISIM.VComponents.all;
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entity xilinx_pcie2wb is
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entity xilinx_pcie2wb is
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generic (
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-- BAR0_WIDTH = 28 sets address space for 2^28 bytes = 256MB, BARO = x"F0000000"
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-- BAR0_WIDTH = 22 sets address space for 2^22 bytes = 4MB, BARO = x"FFC00000"
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BAR0 : bit_vector := x"FFC00000";
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BAR0_WIDTH : integer := 22
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);
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Port ( --FPGA PINS(EXTERNAL):
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Port ( --FPGA PINS(EXTERNAL):
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pci_exp_txp : out std_logic;
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pci_exp_txp : out std_logic;
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pci_exp_txn : out std_logic;
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pci_exp_txn : out std_logic;
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pci_exp_rxp : in std_logic;
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pci_exp_rxp : in std_logic;
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pci_exp_rxn : in std_logic;
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pci_exp_rxn : in std_logic;
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| Line 81... |
Line 89... |
pcie_bar0_wb_ack_i : in std_logic;
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pcie_bar0_wb_ack_i : in std_logic;
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pcie_bar0_wb_clk_o : out std_logic; --62.5MHz
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pcie_bar0_wb_clk_o : out std_logic; --62.5MHz
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pcie_bar0_wb_sel_o : out std_logic_vector(3 downto 0);
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pcie_bar0_wb_sel_o : out std_logic_vector(3 downto 0);
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--OTHER:
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--OTHER:
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pcie_irq : in std_logic;
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pcie_irq : in std_logic;
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pcie_msi_enabled : out std_logic; -- added to monitor if MSI interrupt is enabled
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pcie_resetout : out std_logic --active high
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pcie_resetout : out std_logic --active high
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);
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);
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end xilinx_pcie2wb;
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end xilinx_pcie2wb;
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| Line 211... |
Line 220... |
SIGNAL pcie_tlp_tx_complete : std_logic;
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SIGNAL pcie_tlp_tx_complete : std_logic;
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--this signal added by StBa, AAC Microtec
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--this signal added by StBa, AAC Microtec
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SIGNAL irq_prohibit : std_logic;
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SIGNAL irq_prohibit : std_logic;
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SIGNAL pcieirq_state : std_logic_vector(7 downto 0);
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SIGNAL pcieirq_state : std_logic_vector(2 downto 0);
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SIGNAL txtrn_counter : std_logic_vector(7 downto 0);
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SIGNAL txtrn_counter : std_logic_vector(7 downto 0);
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SIGNAL trn_rx_counter : std_logic_vector(7 downto 0);
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SIGNAL trn_rx_counter : std_logic_vector(7 downto 0);
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SIGNAL cfg_completer_id : std_logic_vector(15 downto 0);
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SIGNAL cfg_completer_id : std_logic_vector(15 downto 0);
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SIGNAL wb0_state : std_logic_vector(7 downto 0);
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SIGNAL wb0_state : std_logic_vector(7 downto 0);
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SIGNAL epif_tx_state : std_logic_vector(7 downto 0);
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SIGNAL epif_tx_state : std_logic_vector(7 downto 0);
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| Line 274... |
Line 283... |
VC0_TOTAL_CREDITS_PD : integer := 211;
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VC0_TOTAL_CREDITS_PD : integer := 211;
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VC0_TOTAL_CREDITS_NPH : integer := 8;
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VC0_TOTAL_CREDITS_NPH : integer := 8;
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VC0_TOTAL_CREDITS_CH : integer := 40;
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VC0_TOTAL_CREDITS_CH : integer := 40;
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VC0_TOTAL_CREDITS_CD : integer := 211;
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VC0_TOTAL_CREDITS_CD : integer := 211;
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VC0_CPL_INFINITE : boolean := TRUE;
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VC0_CPL_INFINITE : boolean := TRUE;
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BAR0 : bit_vector := x"F0000000";
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BAR0 : bit_vector := BAR0; --x"F0000000";
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BAR1 : bit_vector := x"00000000";
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BAR1 : bit_vector := x"00000000";
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BAR2 : bit_vector := x"00000000";
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BAR2 : bit_vector := x"00000000";
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BAR3 : bit_vector := x"00000000";
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BAR3 : bit_vector := x"00000000";
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BAR4 : bit_vector := x"00000000";
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BAR4 : bit_vector := x"00000000";
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BAR5 : bit_vector := x"00000000";
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BAR5 : bit_vector := x"00000000";
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| Line 1152... |
Line 1161... |
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--********** WRITE STATE **********
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--********** WRITE STATE **********
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--initiate WB write(s) (1...N DWORD accesses)
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--initiate WB write(s) (1...N DWORD accesses)
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when "00000010" => --state 2
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when "00000010" => --state 2
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pcie_bar0_wb_addr_o_feed(27 downto 2) <= rxtlp_decodedaddress(27 downto 2) + tlp_datacount -1; --256MBytes size is hardcoded here, by cutting 4-MSB off
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pcie_bar0_wb_addr_o_feed(BAR0_WIDTH-1 downto 2) <= rxtlp_decodedaddress(BAR0_WIDTH-1 downto 2) + tlp_datacount -1; -- BAR0 size is hardcoded here, by cutting MSB's off
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pcie_bar0_wb_addr_o_feed(1 downto 0) <= bit10(1 downto 0);
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pcie_bar0_wb_addr_o_feed(1 downto 0) <= bit10(1 downto 0);
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pcie_bar0_wb_sel_o_feed <= rxtlp_firstdw_be;
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pcie_bar0_wb_sel_o_feed <= rxtlp_firstdw_be;
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pcie_bar0_wb_data_o_feed <= bram_rxtlp_readdata;
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pcie_bar0_wb_data_o_feed <= bram_rxtlp_readdata;
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tlp_state_copy <= tlp_state;
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tlp_state_copy <= tlp_state;
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if (tlp_state_copy = tlp_state) then
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if (tlp_state_copy = tlp_state) then
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Line 1189... |
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--********** READ STATE **********
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--********** READ STATE **********
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--initiate WB read, then go to completion state
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--initiate WB read, then go to completion state
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when "00000011" => --state 3
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when "00000011" => --state 3
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pcie_bar0_wb_addr_o_feed(27 downto 2) <= rxtlp_decodedaddress(27 downto 2) + tlp_datacount -1;
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pcie_bar0_wb_addr_o_feed(BAR0_WIDTH-1 downto 2) <= rxtlp_decodedaddress(BAR0_WIDTH-1 downto 2) + tlp_datacount -1;
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pcie_bar0_wb_addr_o_feed(1 downto 0) <= bit10(1 downto 0);
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pcie_bar0_wb_addr_o_feed(1 downto 0) <= bit10(1 downto 0);
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pcie_bar0_wb_sel_o_feed <= rxtlp_firstdw_be;
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pcie_bar0_wb_sel_o_feed <= rxtlp_firstdw_be;
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tlp_state_copy <= tlp_state;
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tlp_state_copy <= tlp_state;
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if (tlp_state_copy = tlp_state) then
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if (tlp_state_copy = tlp_state) then
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start_read_wb0 <= '0';
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start_read_wb0 <= '0';
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| Line 1197... |
Line 1206... |
if (tlp_payloadsize_dwords = tlp_datacount)then
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if (tlp_payloadsize_dwords = tlp_datacount)then
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tlp_state <= "01111110"; --read completion
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tlp_state <= "01111110"; --read completion
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--bram_txtlp_writeaddress remains the same to capture data in next clock cycle
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--bram_txtlp_writeaddress remains the same to capture data in next clock cycle
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else
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else
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tlp_state <= "00011110"; --one more wb read
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tlp_state <= "00011110"; --one more wb read
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bram_txtlp_writeaddress <= bram_txtlp_writeaddress +1;
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tlp_datacount <= tlp_datacount +1;
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tlp_datacount <= tlp_datacount +1;
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end if;
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end if;
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else
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else
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bram_txtlp_we <= "0";
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bram_txtlp_we <= "0";
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end if;
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end if;
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--* read restart STATE *
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--* read restart STATE *
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when "00011110" => --state 30
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when "00011110" => --state 30
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tlp_state_copy <= tlp_state; -- SC: required to re-trigger additional reads, start_read_wb0 <= '1'
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bram_txtlp_writeaddress <= bram_txtlp_writeaddress +1; -- SC: increment address here (moved)
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tlp_state <= "00000011";
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tlp_state <= "00000011";
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bram_txtlp_we <= "0";
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bram_txtlp_we <= "0";
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--intermediate state before completion (to ensure data latch at address-4)
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--intermediate state before completion (to ensure data latch at address-4)
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when "01111110" => --state 126
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when "01111110" => --state 126
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tlp_state <= "00000100";
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tlp_state <= "00000100";
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| Line 1378... |
Line 1388... |
--prohibit IRQ assert when TLP state machine not idle.
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--prohibit IRQ assert when TLP state machine not idle.
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-- if an IRQ is asserted between a read request and completion, it causes an error in the endpoint block.
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-- if an IRQ is asserted between a read request and completion, it causes an error in the endpoint block.
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-- added by StBa, AAC Microtec, 2012
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-- added by StBa, AAC Microtec, 2012
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irq_prohibit <= not tlpstm_isin_idle;
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irq_prohibit <= not tlpstm_isin_idle;
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-- fixed compatibility with both MSI interrupts and legacy interrupts
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-- added by SC, FRIB, 2016
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pcie_msi_enabled <= cfg_interrupt_msienable;
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process (pciewb_localreset_n, trn_clk, pcie_irq, pcieirq_state,
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process (pciewb_localreset_n, trn_clk, pcie_irq, pcieirq_state,
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cfg_interrupt_rdy_n)
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cfg_interrupt_rdy_n)
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begin
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begin
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if (pciewb_localreset_n='0') then
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if (pciewb_localreset_n='0') then
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pcieirq_state <= "00000000";
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pcieirq_state <= "000";
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cfg_interrupt_n <= '1';
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cfg_interrupt_n <= '1';
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cfg_interrupt_assert_n_1 <= '1';
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cfg_interrupt_assert_n_1 <= '1';
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else
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else
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if (trn_clk'event and trn_clk = '1') then
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if (trn_clk'event and trn_clk = '1') then
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case ( pcieirq_state ) is
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case ( pcieirq_state ) is
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--********** idle STATE **********
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--********** idle STATE **********
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when "00000000" => --state 0
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when "000" => --state 0
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if (pcie_irq = '1' and irq_prohibit = '0') then
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pcieirq_state <= "00000001";
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cfg_interrupt_n <= '0'; --active
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else
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cfg_interrupt_n <= '1'; --inactive
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cfg_interrupt_n <= '1'; --inactive
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cfg_interrupt_assert_n_1 <= '1'; --0=assert, 1=deassert
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if (pcie_irq = '1') then
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pcieirq_state <= "001";
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end if;
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end if;
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--********** wait for not irq_prohibit **********
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when "001" => --state 1
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if (irq_prohibit = '0') then
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pcieirq_state <= "010";
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cfg_interrupt_n <= '0'; --active
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cfg_interrupt_assert_n_1 <= '0'; --0=assert, 1=deassert
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cfg_interrupt_assert_n_1 <= '0'; --0=assert, 1=deassert
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end if;
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--********** assert STATE **********
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--********** assert STATE **********
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when "00000001" => --state 1
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when "010" => --state 2
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cfg_interrupt_n <= '0'; --request INTA assertion
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if (cfg_interrupt_rdy_n ='0') then --ep accepted it
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if (cfg_interrupt_rdy_n ='0') then --ep accepted it
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cfg_interrupt_n <= '1'; --deassert the request
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cfg_interrupt_n <= '1'; --deassert the request
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pcieirq_state <= "00000010";
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cfg_interrupt_assert_n_1 <= '1'; --0=assert, 1=deassert
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else
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pcieirq_state <= "011"; -- wait for IRQ deassert
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cfg_interrupt_n <= '0'; --request INTA assertion
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end if;
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end if;
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--********** (LEGACY) pcie_irq kept asserted STATE **********
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--********** pcie_irq kept asserted STATE **********
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when "011" => --state 3
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when "00000010" => --state 2
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if (pcie_irq='0' and irq_prohibit='0' and cfg_interrupt_msienable='0') then
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if (pcie_irq = '0' and irq_prohibit='0') then --pcie_irq gets deasserted
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pcieirq_state <= "100"; -- LEGACY, pcie_irq gets deasserted
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pcieirq_state <= "00000011";
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end if;
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if (pcie_irq='0' and cfg_interrupt_msienable='1') then
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pcieirq_state <= "000"; -- MSI IRQ, back to IDLE when pcie_irq deasserted
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end if;
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end if;
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cfg_interrupt_n <= '1'; --inactive
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cfg_interrupt_n <= '1'; --inactive
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cfg_interrupt_assert_n_1 <= '1'; --0=assert, 1=deassert
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cfg_interrupt_assert_n_1 <= '1'; --0=assert, 1=deassert
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--********** DEassert STATE **********
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--********** DEassert STATE **********
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when "00000011" => --state 3
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-- below state only used for legacy interrupts
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when "100" => --state 4
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cfg_interrupt_n <= '0'; --request INTA DEassertion
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if (cfg_interrupt_rdy_n ='0') then --ep accepted it
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if (cfg_interrupt_rdy_n ='0') then --ep accepted it
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cfg_interrupt_n <= '1'; --deassert the request
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cfg_interrupt_n <= '1'; --deassert the request
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pcieirq_state <= "00000000";
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pcieirq_state <= "000";
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else
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cfg_interrupt_n <= '0'; --request INTA DEassertion
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end if;
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end if;
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when others => --error
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when others => --error
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pcieirq_state <= "00000000"; --go to state 0
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pcieirq_state <= "000"; --go to state 0
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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