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[/] [pdp1/] [trunk/] [rtl/] [vhdl/] [testtop.vhd] - Diff between revs 3 and 10

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Line 25... Line 25... 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
 
-- simulation model.
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
LIBRARY ieee;
 
LIBRARY ieee;
 
USE ieee.std_logic_1164.ALL;
 
USE ieee.std_logic_1164.ALL;
 
USE ieee.std_logic_unsigned.all;
 
 
 
USE ieee.numeric_std.ALL;
 
USE ieee.numeric_std.ALL;
 
 
 
 
 
 
 
--USE ieee.textio.ALL;
 
 
 
 
 
ENTITY testtop IS
 
ENTITY testtop IS
 
END testtop;
 
END testtop;
 
 
 
 
 
ARCHITECTURE behavior OF testtop IS
 
ARCHITECTURE behavior OF testtop IS
 
 
 
 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    -- Component Declaration for the Unit Under Test (UUT)
 
 
 
 
 
    COMPONENT top
 
    COMPONENT top
 
    PORT(
 
    PORT(
 
         CLK_50M : IN  std_logic;
 
         CLK_50M : IN  std_logic;
 
 
 
         CLK_AUX : IN  std_logic;
 
         LED : OUT  std_logic_vector(7 downto 0);
 
         LED : OUT  std_logic_vector(7 downto 0);
 
         SW : IN  std_logic_vector(3 downto 0);
 
         SW : IN  std_logic_vector(3 downto 0);
 
         AWAKE : OUT  std_logic;
 
         AWAKE : OUT  std_logic;
 
         SPI_MOSI : OUT  std_logic;
 
         SPI_MOSI : OUT  std_logic;
 
         DAC_CS : OUT  std_logic;
 
         DAC_CS : OUT  std_logic;
Line 54... Line 56... 
    END COMPONENT;
 
    END COMPONENT;
 
 
 
 
 
 
 
 
 
   --Inputs
 
   --Inputs
 
   signal CLK_50M : std_logic := '0';
 
   signal CLK_50M : std_logic := '0';
 
 
 
   signal CLK_AUX : std_logic := '0';
 
   signal SW : std_logic_vector(3 downto 0) := (others => '0');
 
   signal SW : std_logic_vector(3 downto 0) := (others => '0');
 
   signal DAC_OUT : std_logic := '0';
 
   signal DAC_OUT : std_logic := '0';
 
 
 
 
 
        --Outputs
 
        --Outputs
 
   signal LED : std_logic_vector(7 downto 0);
 
   signal LED : std_logic_vector(7 downto 0);
Line 66... Line 69... 
   signal DAC_CS : std_logic;
 
   signal DAC_CS : std_logic;
 
   signal SPI_SCK : std_logic;
 
   signal SPI_SCK : std_logic;
 
   signal DAC_CLR : std_logic;
 
   signal DAC_CLR : std_logic;
 
        signal TXD, RXD : std_logic;
 
        signal TXD, RXD : std_logic;
 
 
 
 
 
 
 
        -- UART interface
 
 
 
        COMPONENT Minimal_UART_CORE
 
 
 
        PORT(
 
 
 
                CLOCK : IN std_logic;
 
 
 
                RXD : IN std_logic;
 
 
 
                INP : IN std_logic_vector(7 downto 0);
 
 
 
                WR : IN std_logic;
 
 
 
                OUTP : INOUT std_logic_vector(7 downto 0);
 
 
 
                EOC : OUT std_logic;
 
 
 
                TXD : OUT std_logic;
 
 
 
                EOT : OUT std_logic;
 
 
 
                READY : OUT std_logic
 
 
 
                );
 
 
 
        END COMPONENT;
 
 
 
        signal received_byte, old_received_byte, tx_ready, wrote, byte_request,
 
 
 
                eot : std_logic := '0';
 
 
 
        signal read_byte, write_byte: std_logic_vector(7 downto 0);
 
 
 
 
 
 
 
 
 
   constant CLK_50M_period : time := 20ns;
 
   constant CLK_50M_period : time := 20ns;
 
 
 
   constant CLK_AUX_period : time := 7.5ns;
 
 
 
 
 
        constant bittime : time := 8.680555us; --1s/115200;
 
        constant bittime : time := 8.680555us; --1s/115200;
 
 
 
        constant waittime : time := 20*bittime;
 
 
 
 
 
 
 
   procedure send_byte (bytetosend : in std_logic_vector(7 downto 0);
 
 
 
                                                                signal tx_ready : in std_logic;
 
 
 
                                                                signal eot : in std_logic;
 
 
 
                                                                signal write_byte : out std_logic_vector(7 downto 0);
 
 
 
                                                                signal wrote : out std_logic)
 
 
 
        is
 
 
 
      -- subprogram_declarative_items (constant declarations, variable declarations, etc.)
 
 
 
   begin
 
 
 
--              wait for 100ns;
 
 
 
                wait until rising_edge(CLK_50M) and tx_ready = '1' and eot='0';
 
 
 
                write_byte <= bytetosend;
 
 
 
                wrote <= '1';
 
 
 
                wait until rising_edge(CLK_50M);
 
 
 
                wrote <= '0';
 
 
 
--              wait until eot='0' and tx_ready='1';
 
 
 
 
 
 
 
                -- Without UART, it was something like:
 
 
 
--              RXD <= '0'; wait for bittime;
 
 
 
--              RXD <= bytetosend(0); wait for bittime;
 
 
 
--              RXD <= bytetosend(1); wait for bittime;
 
 
 
--              RXD <= bytetosend(2); wait for bittime;
 
 
 
--              RXD <= bytetosend(3); wait for bittime;
 
 
 
--              RXD <= bytetosend(4); wait for bittime;
 
 
 
--              RXD <= bytetosend(5); wait for bittime;
 
 
 
--              RXD <= bytetosend(6); wait for bittime;
 
 
 
--              RXD <= bytetosend(7); wait for bittime;
 
 
 
--              RXD <= '1'; wait for bittime;           -- first sixbit 000101
 
 
 
--              wait for waittime;
 
 
 
   end send_byte;
 
 
 
 
 
 
 
 
 
BEGIN
 
BEGIN
 
 
 
 
 
        -- Instantiate the Unit Under Test (UUT)
 
        -- Instantiate the Unit Under Test (UUT)
 
   uut: top PORT MAP (
 
   uut: top PORT MAP (
 
          CLK_50M => CLK_50M,
 
          CLK_50M => CLK_50M,
 
 
 
                         CLK_AUX => CLK_AUX,
 
          LED => LED,
 
          LED => LED,
 
          SW => SW,
 
          SW => SW,
 
          AWAKE => AWAKE,
 
          AWAKE => AWAKE,
 
          SPI_MOSI => SPI_MOSI,
 
          SPI_MOSI => SPI_MOSI,
 
          DAC_CS => DAC_CS,
 
          DAC_CS => DAC_CS,
Line 97... Line 154... 
                wait for CLK_50M_period/2;
 
                wait for CLK_50M_period/2;
 
                CLK_50M <= '1';
 
                CLK_50M <= '1';
 
                wait for CLK_50M_period/2;
 
                wait for CLK_50M_period/2;
 
   end process;
 
   end process;
 
 
 
 
 
 
 
   CLK_AUX_process :process
 
 
 
   begin
 
 
 
                CLK_AUX <= '0';
 
 
 
                wait for CLK_AUX_period/2;
 
 
 
                CLK_AUX <= '1';
 
 
 
                wait for CLK_AUX_period/2;
 
 
 
   end process;
 
 
 
 
 
 
 
        -- UART for talking to UUT
 
 
 
        Inst_Minimal_UART_CORE: Minimal_UART_CORE PORT MAP(
 
 
 
                CLOCK => CLK_50M,
 
 
 
 
 
 
 
                EOC => received_byte,   -- end of character; rising edge indicates valid data in OUTP
 
 
 
                OUTP => read_byte,
 
 
 
 
 
 
 
                RXD => TXD,
 
 
 
                TXD => RXD,
 
 
 
 
 
 
 
                EOT => eot,     -- end of transmit; indicates a character has been sent
 
 
 
                INP => write_byte,
 
 
 
                READY => tx_ready,      -- indicates that we may write
 
 
 
                WR => wrote
 
 
 
        );
 
 
 
 
 
   -- Stimulus process
 
   -- Stimulus process
 
   stim_proc: process
 
   stim_proc: process
 
   begin
 
   begin
 
                RXD <= '1';
 
                wait for 1ms;
 
      -- hold reset state for 100ms.
 
                send_byte("10000101", tx_ready, eot, write_byte, wrote);
 
      wait for 10ms;
 
                send_byte("00111111", tx_ready, eot, write_byte, wrote);  -- ignored, as bit 7 is not set
 
 
 
                send_byte("10000110", tx_ready, eot, write_byte, wrote);
 
                                wait for 16*bittime;
 
                send_byte("10111000", tx_ready, eot, write_byte, wrote);  -- Together 050670
 
                -- TODO: show reply data
 
                -- TODO: show reply data
 
                RXD <= '0'; wait for bittime;
 
 
 
                RXD <= '1'; wait for bittime;
 
 
 
                RXD <= '0'; wait for bittime;
 
 
 
                RXD <= '1'; wait for bittime;
 
 
 
                RXD <= '0'; wait for bittime;
 
 
 
                RXD <= '0'; wait for bittime;
 
 
 
                RXD <= '0'; wait for bittime;
 
 
 
                RXD <= '0'; wait for bittime;
 
 
 
                RXD <= '1'; wait for bittime;
 
 
 
                RXD <= '1'; wait for bittime;           -- first sixbit 000101
 
 
 
                wait for 16*bittime;
 
 
 
                RXD <= '0'; wait for bittime;
 
 
 
                RXD <= '1'; wait for bittime;
 
 
 
                RXD <= '1'; wait for bittime;
 
 
 
                RXD <= '1'; wait for bittime;
 
 
 
                RXD <= '1'; wait for bittime;
 
 
 
                RXD <= '1'; wait for bittime;
 
 
 
                RXD <= '1'; wait for bittime;
 
 
 
                RXD <= '0'; wait for bittime;
 
 
 
                RXD <= '0'; wait for bittime;
 
 
 
                RXD <= '1'; wait for bittime;                           -- this byte is not marked as binary data and should be skipped
 
 
 
                wait for 16*bittime;
 
 
 
                RXD <= '0'; wait for bittime;
 
 
 
                RXD <= '0'; wait for bittime;
 
 
 
                RXD <= '1'; wait for bittime;
 
 
 
                RXD <= '1'; wait for bittime;
 
 
 
                RXD <= '0'; wait for bittime;
 
 
 
                RXD <= '0'; wait for bittime;
 
 
 
                RXD <= '0'; wait for bittime;
 
 
 
                RXD <= '0'; wait for bittime;
 
 
 
                RXD <= '1'; wait for bittime;
 
 
 
                RXD <= '1'; wait for bittime;           -- second sixbit 001100
 
 
 
                wait for 16*bittime;
 
 
 
                RXD <= '0'; wait for bittime;
 
 
 
                RXD <= '0'; wait for bittime;
 
 
 
                RXD <= '0'; wait for bittime;
 
 
 
                RXD <= '0'; wait for bittime;
 
 
 
                RXD <= '1'; wait for bittime;
 
 
 
                RXD <= '1'; wait for bittime;
 
 
 
                RXD <= '1'; wait for bittime;
 
 
 
                RXD <= '0'; wait for bittime;
 
 
 
                RXD <= '1'; wait for bittime;
 
 
 
                RXD <= '1'; wait for bittime;           -- third sixbit 111000
 
 
 
 
 
 
 
 
 
 
 
      wait for CLK_50M_period*10;
 
      wait for CLK_50M_period*10;
 
 
 
 
 
      -- insert stimulus here 
      -- insert stimulus here 
 
 
 

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