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[/] [plasma/] [trunk/] [kernel/] [ethernet.c] - Diff between revs 430 and 431

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Rev 430 Rev 431
Line 30... Line 30...
static unsigned char reflect[256];
static unsigned char reflect[256];
static unsigned char reflectNibble[256];
static unsigned char reflectNibble[256];
static OS_Semaphore_t *SemEthernet, *SemEthTransmit;
static OS_Semaphore_t *SemEthernet, *SemEthTransmit;
static int gIndex;          //byte index into 0x13ff0000 receive buffer
static int gIndex;          //byte index into 0x13ff0000 receive buffer
static int gCrcChecked;
static int gCrcChecked;
 
static volatile int ethTxBusy;
 
 
 
 
//Read received data from 0x13ff0000.  Data starts with 0x5d+MACaddress.
//Read received data from 0x13ff0000.  Data starts with 0x5d+MACaddress.
//Data is being received while processing the data.  Therefore,
//Data is being received while processing the data.  Therefore,
//all errors require waiting and then re-processing the data
//all errors require waiting and then re-processing the data
Line 46... Line 47...
   unsigned long crc;
   unsigned long crc;
   int byteCrc;
   int byteCrc;
   volatile unsigned char *buf = (unsigned char*)ETHERNET_RECEIVE;
   volatile unsigned char *buf = (unsigned char*)ETHERNET_RECEIVE;
   int packetExpected;
   int packetExpected;
 
 
 
   while(ethTxBusy)
 
      OS_ThreadSleep(1);
 
 
   //Find the start of a frame
   //Find the start of a frame
   packetExpected = MemoryRead(IRQ_STATUS) & IRQ_ETHERNET_RECEIVE;
   packetExpected = MemoryRead(IRQ_STATUS) & IRQ_ETHERNET_RECEIVE;
   MemoryRead(ETHERNET_REG);        //clear receive interrupt
   MemoryRead(ETHERNET_REG);        //clear receive interrupt
   emptyCount = 0;
   emptyCount = 0;
 
 
Line 152... Line 156...
   int i, byte, shift;
   int i, byte, shift;
   unsigned long crc;
   unsigned long crc;
   volatile unsigned char *buf = (unsigned char*)ETHERNET_TRANSMIT;
   volatile unsigned char *buf = (unsigned char*)ETHERNET_TRANSMIT;
 
 
   OS_SemaphorePend(SemEthTransmit, OS_WAIT_FOREVER);
   OS_SemaphorePend(SemEthTransmit, OS_WAIT_FOREVER);
 
   ethTxBusy = 1;
 
 
   //Wait for previous transfer to complete
   //Wait for previous transfer to complete
   for(i = 0; i < 10000; ++i)
   for(i = 0; i < 10000; ++i)
   {
   {
      if(MemoryRead(IRQ_STATUS) & IRQ_ETHERNET_TRANSMIT)
      if(MemoryRead(IRQ_STATUS) & IRQ_ETHERNET_TRANSMIT)
Line 192... Line 197...
   //Start transfer
   //Start transfer
   length = (length + 12 + 4) >> 2;
   length = (length + 12 + 4) >> 2;
   MemoryWrite(ETHERNET_REG, length);
   MemoryWrite(ETHERNET_REG, length);
   Led(2, 0);
   Led(2, 0);
 
 
 
   //Wait for previous transfer to complete
 
   for(i = 0; i < 10000; ++i)
 
   {
 
      if(MemoryRead(IRQ_STATUS) & IRQ_ETHERNET_TRANSMIT)
 
         break;
 
   }
 
   ethTxBusy = 0;
 
 
   OS_SemaphorePost(SemEthTransmit);
   OS_SemaphorePost(SemEthTransmit);
}
}
 
 
 
 
void EthernetThread(void *arg)
void EthernetThread(void *arg)
Line 388... Line 401...
 
 
   //Start receive DMA
   //Start receive DMA
   MemoryWrite(GPIO0_SET, ETHERNET_ENABLE);
   MemoryWrite(GPIO0_SET, ETHERNET_ENABLE);
}
}
 
 
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