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[/] [plasma/] [trunk/] [vhdl/] [mlite_pack.vhd] - Diff between revs 397 and 429

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Rev 397 Rev 429
Line 161... Line 161... 
   end component;
 
   end component;
 
 
 
 
 
   -- For Xilinx
 
   -- For Xilinx
 
   component RAM16X1D
 
   component RAM16X1D
 
      -- synthesis translate_off 
      -- synthesis translate_off 
      generic (INIT : bit_vector := X"16");
 
      generic (INIT : bit_vector := X"0000");
 
      -- synthesis translate_on 
      -- synthesis translate_on 
      port (DPO   : out STD_ULOGIC;
 
      port (DPO   : out STD_ULOGIC;
 
            SPO   : out STD_ULOGIC;
 
            SPO   : out STD_ULOGIC;
 
            A0    : in STD_ULOGIC;
 
            A0    : in STD_ULOGIC;
 
            A1    : in STD_ULOGIC;
 
            A1    : in STD_ULOGIC;
Line 181... Line 181... 
   end component;
 
   end component;
 
 
 
 
 
   -- For Xilinx Virtex-5
 
   -- For Xilinx Virtex-5
 
   component RAM32X1D
 
   component RAM32X1D
 
      -- synthesis translate_off 
      -- synthesis translate_off 
      generic (INIT : bit_vector := X"32");
 
      generic (INIT : bit_vector := X"00000000");
 
      -- synthesis translate_on 
      -- synthesis translate_on 
      port (DPO   : out STD_ULOGIC;
 
      port (DPO   : out STD_ULOGIC;
 
            SPO   : out STD_ULOGIC;
 
            SPO   : out STD_ULOGIC;
 
            A0    : in STD_ULOGIC;
 
            A0    : in STD_ULOGIC;
 
            A1    : in STD_ULOGIC;
 
            A1    : in STD_ULOGIC;

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