----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- ----
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---- ----
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---- PlTbUtils Example Testcase Architecture for ----
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---- PlTbUtils Example Testcase Architecture for ----
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---- Example Testbench ----
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---- Example Testbench ----
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---- ----
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---- ----
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---- This file is part of the PlTbUtils project ----
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---- This file is part of the PlTbUtils project ----
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---- http://opencores.org/project,pltbutils ----
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---- http://opencores.org/project,pltbutils ----
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---- ----
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---- ----
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---- Description: ----
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---- Description: ----
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---- PlTbUtils is a collection of functions, procedures and ----
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---- PlTbUtils is a collection of functions, procedures and ----
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---- components for easily creating stimuli and checking response ----
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---- components for easily creating stimuli and checking response ----
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---- in automatic self-checking testbenches. ----
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---- in automatic self-checking testbenches. ----
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---- ----
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---- ----
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---- This file is an example which demonstrates how PlTbUtils ----
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---- This file is an example which demonstrates how PlTbUtils ----
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---- can be used. ---- ----
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---- can be used. ---- ----
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---- ----
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---- ----
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---- To Do: ----
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---- To Do: ----
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---- - ----
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---- - ----
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---- ----
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---- ----
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---- Author(s): ----
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---- Author(s): ----
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---- - Per Larsson, pela@opencores.org ----
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---- - Per Larsson, pela.opencores@gmail.com ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- ----
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---- ----
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---- Copyright (C) 2013-2014 Authors and OPENCORES.ORG ----
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---- Copyright (C) 2013-2014 Authors and OPENCORES.ORG ----
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---- ----
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---- ----
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---- This source file may be used and distributed without ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- later version. ----
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---- ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- details. ----
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---- ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.txt_util.all;
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use work.txt_util.all;
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use work.pltbutils_func_pkg.all;
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use work.pltbutils_func_pkg.all;
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-- NOTE: The purpose of the following code is to demonstrate some of the
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-- NOTE: The purpose of the following code is to demonstrate some of the
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-- features of PlTbUtils, not to do a thorough verification.
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-- features of PlTbUtils, not to do a thorough verification.
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architecture tc1 of tc_example2 is
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architecture tc1 of tc_example2 is
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begin
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begin
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p_tc1 : process
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p_tc1 : process
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variable pltbv : pltbv_t := C_PLTBV_INIT;
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variable pltbv : pltbv_t := C_PLTBV_INIT;
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begin
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begin
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startsim("tc1", pltbv, pltbs);
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startsim("tc1", pltbv, pltbs);
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rst <= '1';
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rst <= '1';
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carry_in <= '0';
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carry_in <= '0';
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x <= (others => '0');
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x <= (others => '0');
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y <= (others => '0');
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y <= (others => '0');
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starttest(1, "Reset test", pltbv, pltbs);
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starttest(1, "Reset test", pltbv, pltbs);
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waitclks(2, clk, pltbv, pltbs);
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waitclks(2, clk, pltbv, pltbs);
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check("Sum during reset", sum, 0, pltbv, pltbs);
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check("Sum during reset", sum, 0, pltbv, pltbs);
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check("Carry out during reset", carry_out, '0', pltbv, pltbs);
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check("Carry out during reset", carry_out, '0', pltbv, pltbs);
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rst <= '0';
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rst <= '0';
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endtest(pltbv, pltbs);
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endtest(pltbv, pltbs);
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starttest(2, "Simple sum test", pltbv, pltbs);
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starttest(2, "Simple sum test", pltbv, pltbs);
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carry_in <= '0';
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carry_in <= '0';
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x <= std_logic_vector(to_unsigned(1, x'length));
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x <= std_logic_vector(to_unsigned(1, x'length));
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y <= std_logic_vector(to_unsigned(2, x'length));
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y <= std_logic_vector(to_unsigned(2, x'length));
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waitclks(2, clk, pltbv, pltbs);
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waitclks(2, clk, pltbv, pltbs);
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check("Sum", sum, 3, pltbv, pltbs);
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check("Sum", sum, 3, pltbv, pltbs);
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check("Carry out", carry_out, '0', pltbv, pltbs);
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check("Carry out", carry_out, '0', pltbv, pltbs);
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endtest(pltbv, pltbs);
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endtest(pltbv, pltbs);
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starttest(3, "Simple carry in test", pltbv, pltbs);
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starttest(3, "Simple carry in test", pltbv, pltbs);
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print(G_DISABLE_BUGS=0, pltbv, pltbs, "Bug here somewhere");
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print(G_DISABLE_BUGS=0, pltbv, pltbs, "Bug here somewhere");
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carry_in <= '1';
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carry_in <= '1';
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x <= std_logic_vector(to_unsigned(1, x'length));
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x <= std_logic_vector(to_unsigned(1, x'length));
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y <= std_logic_vector(to_unsigned(2, x'length));
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y <= std_logic_vector(to_unsigned(2, x'length));
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waitclks(2, clk, pltbv, pltbs);
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waitclks(2, clk, pltbv, pltbs);
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check("Sum", sum, 4, pltbv, pltbs);
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check("Sum", sum, 4, pltbv, pltbs);
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check("Carry out", carry_out, '0', pltbv, pltbs);
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check("Carry out", carry_out, '0', pltbv, pltbs);
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print(G_DISABLE_BUGS=0, pltbv, pltbs, "");
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print(G_DISABLE_BUGS=0, pltbv, pltbs, "");
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endtest(pltbv, pltbs);
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endtest(pltbv, pltbs);
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starttest(4, "Simple carry out test", pltbv, pltbs);
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starttest(4, "Simple carry out test", pltbv, pltbs);
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carry_in <= '0';
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carry_in <= '0';
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x <= std_logic_vector(to_unsigned(2**G_WIDTH-1, x'length));
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x <= std_logic_vector(to_unsigned(2**G_WIDTH-1, x'length));
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y <= std_logic_vector(to_unsigned(1, x'length));
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y <= std_logic_vector(to_unsigned(1, x'length));
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waitclks(2, clk, pltbv, pltbs);
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waitclks(2, clk, pltbv, pltbs);
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check("Sum", sum, 0, pltbv, pltbs);
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check("Sum", sum, 0, pltbv, pltbs);
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check("Carry out", carry_out, '1', pltbv, pltbs);
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check("Carry out", carry_out, '1', pltbv, pltbs);
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endtest(pltbv, pltbs);
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endtest(pltbv, pltbs);
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endsim(pltbv, pltbs, true);
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endsim(pltbv, pltbs, true);
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wait;
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wait;
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end process p_tc1;
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end process p_tc1;
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end architecture tc1;
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end architecture tc1;
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