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PWM user manual
Author: Zhu Xu
HYPERLINK "mailto:M99a1@yahoo.cn" M99a1@yahoo.cn
Features
Work as one PWM or one timer.
16 bits main counter.
PWM/Timer can choose between Wishbone interface clock or external clock as working clock.
PWM can choose between dedicated duty cycle input or internal register as source of duty cycle.
Duty cycle and period can be changed at runtime.
Hosted through Wishbone slave interface.
Working clock can be down clocked to at most 1/65535 or EMBED Equation.3 of original frequency.
Period register also serves as timer target register when module is in timer mode.
Operations
All operations of this PWM core is controlled by manipulating registers inside the core through WISHBONE slave interface. The interface is Wishbone B4 compliant.
PWM mode
When mode selection bit (ctrl bit 1) is set the core is in PWM mode. Port o_pwm will output PWM signal continuously when main counter enable bit (ctrl bit 2) and PWM signal output enable bit (ctrl bit 4) are set. It2 s p e r i o d i s s t o r e d i n r e g i s t e r p e r i o d . S i g n a l s c o m i n g f r o m r e g i s t e r D C o r p o r t i _ D C c a n b e u s e d a s d u t y c y c l e . B o t h p e r i o d a n d d u t y c y c l e a r e d e f i n e d b y n u m b e r o f c l o c k c y c l e s . W h e n m a i n c o u n t e r e n a b l e b i t i s r e s e t t h e m a i n c o u n t e r w i l l s t o p r u n n i n g a n d o _pwm will stop changing until the main counter enable bit is set again or the counter logic is reset by external reset or main counter reset bit (ctrl bit 7).
Timer mode
When mode selection bit (ctrl bit 1) is reset the core is in timer mode. Right after main counter enable bit (ctrl bit 2) is set the main counter starts to increment. When the number stores in main counter reaches or exceeds the number stored in register period an interrupt is generated and output through o_pwm. Then the main counter will b e r e s e t . I f c o n t i n u o u s r u n ( c t r l b i t 3 ) i s s e l e c t e d a n d m a i n c o u n t e r e n a b l e b i t i s s e t t h e m a i n c o u n t e r w i l l s t a r t t o i n c r e m e n t a g a i n n o m a t e r w h e t h e r i n t e r r u p t i s c l e a r e d o r n o t . I f n o t m a i n c o u n t e r w o n 2 t s t a r t a g a i n u n t i l i n t e r r u p t i s c l e a r e d .
D o w n c l o cking
Clock for incrementing the main counter can be down clocked before entering main counter logic. Frequency can be divided by odd or even number. Divisor is stored in 16-bit register. If divisor equals 0 or 1, no down clocking is performed. Else output frequency is original frequency/divisor.
Main counter reset
Main counter can be reset by system reset or by setting ctrl bit 7. When changing from PWM mode to timer mode main counter must be reset before timer starts.
Interrupt
In timer mode, when main counter exceeds period an interrupt will be generated. A low to high transition on port o_pwm and set of ctrl bit 5 indicate the interrupt request. Interrupt is cleared by writing 0 to ctrl bit 5.
Control registers
All 4 control registers are accessible through Wishbone slave interface.
NameAddressWidthAccessDescriptionCtrlBase + 08R/W C o r e 2 s o p e r a t i o n c o n t r o l r e g i s t e r D i v i s o r B a s e + 2 1 6 R / W S t o r e s d i v i s o r f o r d o w n c l o c k i n g . P e r i o d B a s e + 4 1 6 R / W S t o r e s p e r i o d d e f i n e d b y n u m b e r o f c l o c k c y c l e s . A l s o u s e d a s t i m e r t a r g e t w h e n w o r k i n g i n t i m e r m o d e . D C B a s e + 6 1 6 R / W S t o r e s d u t y c y c l e defined by number of clock cycles during the pulse.
Ctrl/Operation control register
BitResetDescriptionBit 00When set, external clock is chosen for PWM/timer. When cleared, wb clock is used for PWM/timer.Bit 10When set, PWM is enabled. When cleared, timer is enabled.Bit 20When set, PWM/timer starts. When cleared, PWM/timer stops.Bit 30When set, timer runs continuously. When cleared, timer runs one time.Bit 40When set, o_pwm enabled.Bit 50timer interrupt bit
When it is written with 0, interrupt request is cleared.Bit 60When set, a 16-bit external signal i_DC is used as duty cycle. When cleared, register DC is used.Bit 70When set, main counter resets, o_pwm and crtl bit 5 are also reset. When changing from PWM mode to timer mode main counter reset is needed before timer starts.
Interfaces
Wishbone Slave Interface
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PWM user manual
Author: Zhu Xu
HYPERLINK "mailto:M99a1@yahoo.cn" M99a1@yahoo.cn
Features
Work as one PWM or one timer.
16 bits main counter.
PWM/Timer can choose between Wishbone interface clock or external clock as working clock.
PWM can choose between dedicated duty cycle input or internal register as source of duty cycle.
Duty cycle and period can be changed at runtime.
Hosted through Wishbone slave interface.
Working clock can be down clocked to at most 1/65535 or EMBED Equation.3 of original frequency.
Period register also serves as timer target register when module is in timer mode.
Operations
All operations of this PWM core is controlled by manipulating registers inside the core through WISHBONE slave interface. The interface is Wishbone B4 compliant.
PWM mode
When mode selection bit (ctrl bit 1) is set the core is in PWM mode. Port o_pwm will output PWM signal continuously when main counter enable bit (ctrl bit 2) and PWM signal output enable bit (ctrl bit 4) are set. It2 s p e r i o d i s s t o r e d i n r e g i s t e r p e r i o d . S i g n a l s c o m i n g f r o m r e g i s t e r D C o r p o r t i _ D C c a n b e u s e d a s d u t y c y c l e . B o t h p e r i o d a n d d u t y c y c l e a r e d e f i n e d b y n u m b e r o f c l o c k c y c l e s . W h e n m a i n c o u n t e r e n a b l e b i t i s r e s e t t h e m a i n c o u n t e r w i l l s t o p r u n n i n g a n d o _pwm will stop changing until the main counter enable bit is set again or the counter logic is reset by external reset or main counter reset bit (ctrl bit 7).
Timer mode
When mode selection bit (ctrl bit 1) is reset the core is in timer mode. Right after main counter enable bit (ctrl bit 2) is set the main counter starts to increment. When the number stores in main counter reaches or exceeds the number stored in register period an interrupt is generated and output through o_pwm. Then the main counter will b e r e s e t . I f c o n t i n u o u s r u n ( c t r l b i t 3 ) i s s e l e c t e d a n d m a i n c o u n t e r e n a b l e b i t i s s e t t h e m a i n c o u n t e r w i l l s t a r t t o i n c r e m e n t a g a i n n o m a t e r w h e t h e r i n t e r r u p t i s c l e a r e d o r n o t . I f n o t m a i n c o u n t e r w o n 2 t s t a r t a g a i n u n t i l i n t e r r u p t i s c l e a r e d .
D o w n c l o cking
Clock for incrementing the main counter can be down clocked before entering main counter logic. Frequency can be divided by odd or even number. Divisor is stored in 16-bit register. If divisor equals 0 or 1, no down clocking is performed. Else, the output frequency is original frequency/divisor.
Main counter reset
Main counter can be reset by system reset or by setting ctrl bit 7. When changing from PWM mode to timer mode main counter must be reset before timer starts.
Interrupt
In timer mode, when main counter exceeds period an interrupt will be generated. A low to high transition on port o_pwm and set of ctrl bit 5 indicate the interrupt request. Interrupt is cleared by writing 0 to ctrl bit 5.
Control registers
All 4 control registers are accessible through Wishbone slave interface.
NameAddressWidthAccessDescriptionCtrlBase + 08R/W C o r e 2 s o p e r a t i o n c o n t r o l r e g i s t e r D i v i s o r B a s e + 2 1 6 R / W S t o r e s d i v i s o r f o r d o w n c l o c k i n g . P e r i o d B a s e + 4 1 6 R / W S t o r e s p e r i o d d e f i n e d b y n u m b e r o f c l o c k c y c l e s . A l s o u s e d a s t i m e r t a r g e t w h e n w o r k i n g i n t i m e r m o d e . D C B a s e + 6 1 6 R / W S t o r e s d u t y c y c l e defined by number of clock cycles during the pulse.
Ctrl/Operation control register
BitResetDescriptionBit 00When set, external clock is chosen for PWM/timer. When cleared, wb clock is used for PWM/timer.Bit 10When set, PWM is enabled. When cleared, timer is enabled.Bit 20When set, PWM/timer starts. When cleared, PWM/timer stops.Bit 30When set, timer runs continuously. When cleared, timer runs one time.Bit 40When set, o_pwm enabled.Bit 50timer interrupt bit
When it is written with 0, interrupt request is cleared.Bit 60When set, a 16-bit external signal i_DC is used as duty cycle. When cleared, register DC is used.Bit 70When set, main counter resets, o_pwm and crtl bit 5 are also reset. When changing from PWM mode to timer mode main counter reset is needed before timer starts.
Interfaces
Wishbone Slave Interface
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