Timing and usage after synthesis reported for Xilinx Artix7 (XC7A100T-2csg324) with bits=16 and dithering=5. Xilinx ISE 14.7 was used, with default settings. No optimizations of any parameters or tool settings were applied. Also, all of the code is in pure VHDL, and no Xilinx specific IP blocks or hard macros have been used.
Timing and usage after synthesis reported for Xilinx Artix7 (XC7A100T-2csg324) with bits=16 and dithering=5. Xilinx ISE 14.7 was used, with default settings. No optimizations of any parameters or tool settings were applied. Also, all of the code is in pure VHDL, and no Xilinx specific IP blocks or hard macros have been used.
Summary:
minimal ineq reg p_small pipelined
LUTs 36 43 35 40 49
REGs 17 17 30 31 43
MHz 259 211 382 437 483
sensitive yes no no no no
latency none none 1sc 1sc+1c 1sc+2c
Where sensitive means that the implementation can produce incorrect output for a short duration during input value change, and latency units are sc = subcycle, c = clock cycle.
