OpenCores
URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

[/] [qaz_libs/] [trunk/] [BFM/] [src/] [tb/] [tb_base.sv] - Diff between revs 34 and 50

Show entire file | Details | Blame | View Log

Rev 34 Rev 50
Line 1... Line 1...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2019 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
Line 23... Line 23...
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
`timescale 1ps/1ps
 
 
 
import tb_clk_pkg::*;
 
 
 
 
 
module
module
  tb_base
  tb_base
  #(
  #(
    parameter PERIOD = 0,
    N = 1,
    parameter ASSERT_TIME = 0
    realtime PERIODS[N],
 
    realtime ASSERT_TIME = (PERIODS[0] * 5) + (PERIODS[0] / 3)
  )
  )
  (
  (
    output      clock,
    output bit tb_clk[N],
    output reg  reset
    output bit tb_aresetn,
 
    output bit tb_reset[N]
  );
  );
 
  timeunit 1ns;
 
  timeprecision 100ps;
 
 
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  function void assert_reset(realtime reset_assert=ASSERT_TIME);
  task assert_reset
 
  (
 
    input time reset_assert
 
  );
 
 
 
    reset = 1;
 
    $display( "-#- %16.t | %m | reset asserted!", $time );
 
 
 
    #reset_assert;
 
 
 
    reset = 0;
 
    $display( "-#- %16.t | %m | reset deasserted!", $time );
 
 
 
endtask
 
 
 
 
 
  // --------------------------------------------------------------------
 
  //
 
  task timeout_stop
 
  (
 
    input time timeout
 
  );
 
 
 
    $display("-#- %16.t | %m | timeout_stop at %t", $time, timeout);
 
 
 
    fork
    fork
      #(timeout) $stop;
      begin
 
      tb_aresetn = 0;
 
      #reset_assert;
 
      tb_aresetn = 1;
 
      end
    join_none
    join_none
 
  endfunction
 
 
endtask
  // --------------------------------------------------------------------
 
  bit disable_clks[N];
 
 
 
  generate
 
    for(genvar j = 0; j < N; j++) begin
 
      always
 
        if(disable_clks[j])
 
          tb_clk[j] = 0;
 
        else
 
          #(PERIODS[j]/2) tb_clk[j] = ~tb_clk[j];
 
    end
 
  endgenerate
 
 
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  generate
  tb_clk_class tb_clk_c;
    for(genvar j = 0; j < N; j++) begin
  tb_clk_if tb_clk_driver();
      bit reset = 1;
  assign clock = tb_clk_driver.clk;
      assign tb_reset[j] = reset;
  time reset_assert = (PERIOD * 5) + (PERIOD / 3);
 
  logic init_done = 0;
 
 
 
  initial
 
    begin
 
 
 
 
      always @(posedge tb_clk[j] or negedge tb_aresetn)
 
        if(~tb_aresetn)
      reset = 1;
      reset = 1;
 
        else
      tb_clk_c = new( tb_clk_driver );
          reset = 0;
 
 
      if( PERIOD != 0 )
 
        tb_clk_c.init_basic_clock( PERIOD );
 
 
 
      if( ASSERT_TIME != 0 )
 
        assert_reset( ASSERT_TIME );
 
      else if( reset_assert != 0 )
 
        assert_reset( reset_assert );
 
 
 
      init_done = 1;
 
 
 
    end
    end
endmodule
  endgenerate
 
 
 
  // --------------------------------------------------------------------
 
  initial
 
    assert_reset();
 
 
 
// --------------------------------------------------------------------
 
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.