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[/] [qaz_libs/] [trunk/] [PCIe/] [sim/] [tests/] [tb_riffa_register_file/] [tb_riffa_register_file.sv] - Diff between revs 34 and 40

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Rev 34 Rev 40
Line 50... Line 50...
  import tb_riffa_register_file_pkg::*;
  import tb_riffa_register_file_pkg::*;
 
 
 
 
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  //
  riffa_chnl_if #(.N(N)) chnl_in(.*);
  riffa_chnl_if #(.N(N)) chnl_bus(.*);
  riffa_register_if #(.N(N), .B(B)) r_if(.*); // dword sized (32 bit) registers
  riffa_register_if #(.N(N), .B(B)) r_if(.*); // dword sized (32 bit) registers
 
 
 
 
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  //
Line 77... Line 77...
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  //
  tb_riffa_register_file_class #(.N(N)) a_h;
  tb_riffa_register_file_class #(.N(N)) a_h;
 
 
  initial
  initial
    a_h = new(chnl_in);
    a_h = new(chnl_bus);
 
 
 
 
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  //
  int rx_count = 0;
  int rx_count = 0;
  wire rx_en = chnl_in.rx_data_valid & chnl_in.rx_data_ren;
  wire rx_en = chnl_bus.rx_data_valid & chnl_bus.rx_data_ren;
 
 
  always_ff @(posedge chnl_in.rx_clk)
  always_ff @(posedge chnl_bus.rx_clk)
    if(chnl_in.rx)
    if(chnl_bus.rx)
    begin
    begin
      if(rx_en)
      if(rx_en)
        rx_count++;
        rx_count++;
    end
    end
    else
    else
Line 98... Line 98...
 
 
 
 
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  //
  int tx_count = 0;
  int tx_count = 0;
  wire tx_en = chnl_in.tx_data_valid & chnl_in.tx_data_ren;
  wire tx_en = chnl_bus.tx_data_valid & chnl_bus.tx_data_ren;
 
 
  always_ff @(posedge chnl_in.tx_clk)
  always_ff @(posedge chnl_bus.tx_clk)
    if(chnl_in.tx)
    if(chnl_bus.tx)
    begin
    begin
      if(tx_en)
      if(tx_en)
        tx_count++;
        tx_count++;
    end
    end
    else
    else

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