//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2017 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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module
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module
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riffa_axis_test_pattern
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riffa_axis_test_pattern
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#(
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#(
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N, // RIFFA data bus width in bytes
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N, // RIFFA data bus width in bytes
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W = 4, // word width in bytes
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W = 4, // word width in bytes
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WPB = N / W // number of words per beat
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WPB = N / W // number of words per beat
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)
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)
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(
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(
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riffa_chnl_if chnl_in,
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riffa_chnl_if chnl_bus,
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input [31:0] tx_len,
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input [31:0] tx_len,
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input clk,
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input clk,
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input reset
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input reset
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);
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);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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localparam I = 0; // TID width
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localparam I = 0; // TID width
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localparam D = 0; // TDEST width
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localparam D = 0; // TDEST width
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localparam U = 3; // TUSER width
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localparam U = 3; // TUSER width
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localparam RW = (N/4); // width of the RIFFA bus in 32 bit words
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localparam RW = (N/4); // width of the RIFFA bus in 32 bit words
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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wire aclk = clk;
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wire aclk = clk;
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wire aresetn = ~reset;
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wire aresetn = ~reset;
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out(.*);
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axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out(.*);
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axis_test_patern #(.N(N), .W(W), .WPB(WPB))
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axis_test_patern #(.N(N), .W(W), .WPB(WPB))
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axis_test_patern_i(.*);
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axis_test_patern_i(.*);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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wire tx_ready = 1;
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wire tx_ready = 1;
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wire tx_last = 1;
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wire tx_last = 1;
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wire acked;
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wire acked;
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wire [30:0] tx_off = 0;
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wire [30:0] tx_off = 0;
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wire [30:0] tx_index;
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wire [30:0] tx_index;
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wire tx_done = (tx_index >= tx_len - RW);
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wire tx_done = (tx_index >= tx_len - RW);
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riffa_chn_tx #(.N(N))
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riffa_chn_tx #(.N(N))
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riffa_chn_tx_i(.*);
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riffa_chn_tx_i(.*);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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assign axis_out.tready = chnl_in.tx_data_ren & acked;
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assign axis_out.tready = chnl_bus.tx_data_ren & acked;
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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assign chnl_in.rx_clk = clk;
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assign chnl_bus.rx_clk = clk;
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assign chnl_in.tx_clk = clk;
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assign chnl_bus.tx_clk = clk;
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assign chnl_in.rx_reset = reset;
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assign chnl_bus.rx_reset = reset;
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assign chnl_in.tx_reset = reset;
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assign chnl_bus.tx_reset = reset;
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assign chnl_in.tx_last = tx_last;
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assign chnl_bus.tx_last = tx_last;
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assign chnl_in.tx_len = tx_len;
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assign chnl_bus.tx_len = tx_len;
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assign chnl_in.tx_off = tx_off;
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assign chnl_bus.tx_off = tx_off;
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assign chnl_in.tx_data_valid = axis_out.tvalid & acked;
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assign chnl_bus.tx_data_valid = axis_out.tvalid & acked;
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assign chnl_in.tx_data = axis_out.tdata;
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assign chnl_bus.tx_data = axis_out.tdata;
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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endmodule
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endmodule
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