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[/] [qaz_libs/] [trunk/] [PCIe/] [src/] [RIFFA/] [riffa_chnl_rx_fsm.sv] - Diff between revs 32 and 35

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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
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//// Copyright (C) 2017 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG                 ////
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//// the original copyright notice and the associated disclaimer. ////
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//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
module
module
  riffa_chnl_rx_fsm
  riffa_chnl_rx_fsm
  (
  (
    input   rx,
    input   rx,
    input   rx_data_valid,
    input   rx_data_valid,
 
    input   rx_ready,
    output  rx_ack,
    output  rx_ack,
    output  rx_done,
    output  rx_done,
    input   reset,
    input   reset,
    input   clk
    input   clk
  );
  );
  //---------------------------------------------------
  //---------------------------------------------------
  //  state machine binary definitions
  //  state machine binary definitions
  enum reg [4:0]
  enum reg [4:0]
    {
    {
      IDLE    = 5'b0_0001,
      IDLE    = 5'b0_0001,
      ACK     = 5'b0_0010,
      ACK     = 5'b0_0010,
      RX      = 5'b0_0100,
      RX      = 5'b0_0100,
      PENDING = 5'b0_1000,
      PENDING = 5'b0_1000,
      ERROR   = 5'b1_0000
      ERROR   = 5'b1_0000
    } state, next_state;
    } state, next_state;
  //---------------------------------------------------
  //---------------------------------------------------
  //  state machine flop
  //  state machine flop
  always_ff @(posedge clk)
  always_ff @(posedge clk)
    if(reset)
    if(reset)
      state <= IDLE;
      state <= IDLE;
    else
    else
      state <= next_state;
      state <= next_state;
  //---------------------------------------------------
  //---------------------------------------------------
  //  state machine
  //  state machine
  always_comb
  always_comb
    case(state)
    case(state)
      IDLE:     if(rx)
      IDLE:     if(rx)
                  next_state <= ACK;
                  next_state <= ACK;
                else
                else
                  next_state <= IDLE;
                  next_state <= IDLE;
 
 
      ACK:      next_state <= RX;
      // ACK:      next_state <= RX;
 
      ACK:      if(rx_ready)
 
                  next_state <= RX;
 
                else
 
                  next_state <= ACK;
 
 
      RX:       if(rx)
      RX:       if(rx)
                  next_state <= RX;
                  next_state <= RX;
                else if(rx_data_valid)
                else if(rx_data_valid)
                  next_state <= PENDING;
                  next_state <= PENDING;
                else
                else
                  next_state <= IDLE;
                  next_state <= IDLE;
      PENDING:  if(rx_data_valid)
      PENDING:  if(rx_data_valid)
                  next_state <= PENDING;
                  next_state <= PENDING;
                else
                else
                  next_state <= IDLE;
                  next_state <= IDLE;
      ERROR:    next_state <= IDLE;
      ERROR:    next_state <= IDLE;
      default:  next_state <= ERROR;
      default:  next_state <= ERROR;
    endcase
    endcase
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  //
  assign rx_ack = (state == ACK);
  assign rx_ack = (state == ACK);
  assign rx_done = (state != IDLE) & (next_state == IDLE);
  assign rx_done = (state != IDLE) & (next_state == IDLE);
// --------------------------------------------------------------------
// --------------------------------------------------------------------
//
//
endmodule
endmodule
 
 

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