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[/] [qaz_libs/] [trunk/] [PCIe/] [src/] [RIFFA/] [riffa_chnl_tx.sv] - Diff between revs 32 and 34

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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
module
module
  riffa_chn_tx
  riffa_chn_tx
  #(
  #(
    N, // data bus width in bytes
    N // data bus width in bytes
    D = 2 // TX data fifo depth
 
  )
  )
  (
  (
    riffa_chnl_if chnl_in,
    riffa_chnl_if chnl_in,
    input tx_ready,
    input tx_ready,
    input tx_done,
    input tx_done,
    output reg [31:0] tx_index,
    output acked,
 
    output reg [30:0] tx_index,
    input tx_last,
    input tx_last,
    input [31:0] tx_len,
    input [31:0] tx_len,
    input [30:0] tx_off,
    input [30:0] tx_off,
 
 
    input clk,
    input clk,
    input reset
    input reset
  );
  );
 
 
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  //
  localparam RW = (N/4); // width of the bus in 32 bit words
 
 
 
 
 
  // --------------------------------------------------------------------
 
  //
 
  riffa_chnl_tx_fsm
  riffa_chnl_tx_fsm
    riffa_chnl_tx_fsm_i
    riffa_chnl_tx_fsm_i
    (
    (
      .tx(chnl_in.tx),
      .tx(chnl_in.tx),
      .tx_ack(chnl_in.tx_ack),
      .tx_ack(chnl_in.tx_ack),
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  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  //
  always_ff @(posedge clk)
  always_ff @(posedge clk)
    if(reset | ~chnl_in.tx)
    if(reset | ~chnl_in.tx | tx_done)
      tx_index = 0;
      tx_index = 0;
    else if(chnl_in.tx_data_valid & chnl_in.tx_data_ren)
    else if(chnl_in.tx_data_valid & chnl_in.tx_data_ren)
      tx_index <= tx_index + RW;
      tx_index <= tx_index + (N/4); // increment by 32 bit words
 
 
 
 
// --------------------------------------------------------------------
// --------------------------------------------------------------------
//
//
endmodule
endmodule

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