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[/] [qaz_libs/] [trunk/] [PCIe/] [src/] [RIFFA/] [riffa_register_file.sv] - Diff between revs 37 and 39

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Rev 37 Rev 39
Line 30... Line 30...
  #(
  #(
    N, //  data bus width in bytes
    N, //  data bus width in bytes
    B // number of register banks
    B // number of register banks
  )
  )
  (
  (
    riffa_chnl_if chnl_in,
    riffa_chnl_if chnl_bus,
    riffa_register_if r_if,
    riffa_register_if r_if,
    input clk,  // must be same clock domain as rx_clk & tx_clk
    input clk,  // must be same clock domain as rx_clk & tx_clk
    input reset // must be same clock domain as rx_clk & tx_clk
    input reset // must be same clock domain as rx_clk & tx_clk
  );
  );
 
 
Line 67... Line 67...
  wire rd_empty;
  wire rd_empty;
  wire [(8*N)-1:0] rd_data;
  wire [(8*N)-1:0] rd_data;
  wire rd_en;
  wire rd_en;
 
 
  riffa_chn_rx #(.N(N))
  riffa_chn_rx #(.N(N))
    riffa_chn_rx_i(.chnl_bus(chnl_in), .*);
    riffa_chn_rx_i(.chnl_bus(chnl_bus), .*);
 
 
 
 
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  //
  wire register_select [RC-1:0];
  wire register_select [RC-1:0];
Line 95... Line 95...
  endgenerate
  endgenerate
 
 
 
 
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  //
  // assign chnl_in.rx_data_ren = rx_data_ren;
  // assign chnl_bus.rx_data_ren = rx_data_ren;
  assign rd_en = ~rd_empty;
  assign rd_en = ~rd_empty;
 
 
 
 
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  //
Line 108... Line 108...
  wire tx_last = 1;
  wire tx_last = 1;
  wire acked;
  wire acked;
  wire [31:0] tx_len = RC;
  wire [31:0] tx_len = RC;
  wire [30:0] tx_off = 0;
  wire [30:0] tx_off = 0;
  wire [30:0] tx_index;
  wire [30:0] tx_index;
  wire tx_done = (tx_index >= chnl_in.tx_len - RW);
  wire tx_done = (tx_index >= chnl_bus.tx_len - RW);
 
 
  riffa_chn_tx #(.N(N))
  riffa_chn_tx #(.N(N))
    riffa_chn_tx_i(.*);
    riffa_chn_tx_i(.*);
 
 
 
 
Line 135... Line 135...
  //
  //
  recursive_mux #(.A($clog2(B)), .W(N*8))
  recursive_mux #(.A($clog2(B)), .W(N*8))
    recursive_mux_i
    recursive_mux_i
    (
    (
      .select(tx_index[$clog2(B) + $clog2(RW) - 1:$clog2(RW)]),
      .select(tx_index[$clog2(B) + $clog2(RW) - 1:$clog2(RW)]),
      .data_out(chnl_in.tx_data),
      .data_out(chnl_bus.tx_data),
      .*
      .*
    );
    );
 
 
 
 
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  //
  assign chnl_in.rx_clk = clk;
  assign chnl_bus.rx_clk = clk;
  assign chnl_in.tx_clk = clk;
  assign chnl_bus.tx_clk = clk;
  assign chnl_in.rx_reset = reset;
  assign chnl_bus.rx_reset = reset;
  assign chnl_in.tx_reset = reset;
  assign chnl_bus.tx_reset = reset;
  assign chnl_in.tx_last = 1;
  assign chnl_bus.tx_last = 1;
  assign chnl_in.tx_len = RC;
  assign chnl_bus.tx_len = RC;
  assign chnl_in.tx_off = 0;
  assign chnl_bus.tx_off = 0;
  assign chnl_in.tx_data_valid = acked;
  assign chnl_bus.tx_data_valid = acked;
 
 
 
 
// --------------------------------------------------------------------
// --------------------------------------------------------------------
//
//
endmodule
endmodule

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