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[/] [qaz_libs/] [trunk/] [axi4_lib/] [src/] [axi4_if.sv] - Diff between revs 29 and 31

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Rev 29 Rev 31
Line 36... Line 36...
  (
  (
    input           aresetn,
    input           aresetn,
    input           aclk
    input           aclk
  );
  );
 
 
  logic [(A-1):0]    araddr;
  wire [(A-1):0]    araddr;
  logic [1:0]        arburst;
  wire [1:0]        arburst;
  logic [3:0]        arcache;
  wire [3:0]        arcache;
  logic [(I-1):0]    arid;
  wire [(I-1):0]    arid;
  logic [7:0]        arlen;
  wire [7:0]        arlen;
  logic              arlock;
  wire              arlock;
  logic [2:0]        arprot;
  wire [2:0]        arprot;
  logic [3:0]        arqos;
  wire [3:0]        arqos;
  logic              arready;
  wire              arready;
  logic [3:0]        arregion;
  wire [3:0]        arregion;
  logic [2:0]        arsize;
  wire [2:0]        arsize;
  logic              arvalid;
  wire              arvalid;
  logic [(A-1):0]    awaddr;
  wire [(A-1):0]    awaddr;
  logic [1:0]        awburst;
  wire [1:0]        awburst;
  logic [3:0]        awcache;
  wire [3:0]        awcache;
  logic [(I-1):0]    awid;
  wire [(I-1):0]    awid;
  logic [7:0]        awlen;
  wire [7:0]        awlen;
  logic              awlock;
  wire              awlock;
  logic [2:0]        awprot;
  wire [2:0]        awprot;
  logic [3:0]        awqos;
  wire [3:0]        awqos;
  logic              awready;
  wire              awready;
  logic [3:0]        awregion;
  wire [3:0]        awregion;
  logic [2:0]        awsize;
  wire [2:0]        awsize;
  logic              awvalid;
  wire              awvalid;
  logic [(I-1):0]    bid;
  wire [(I-1):0]    bid;
  logic              bready;
  wire              bready;
  logic [1:0]        bresp;
  wire [1:0]        bresp;
  logic              bvalid;
  wire              bvalid;
  logic [(8*N)-1:0]  rdata;
  wire [(8*N)-1:0]  rdata;
  logic [(I-1):0]    rid;
  wire [(I-1):0]    rid;
  logic              rlast;
  wire              rlast;
  logic              rready;
  wire              rready;
  logic [1:0]        rresp;
  wire [1:0]        rresp;
  logic              rvalid;
  wire              rvalid;
  logic [(8*N)-1:0]  wdata;
  wire [(8*N)-1:0]  wdata;
  logic [(I-1):0]    wid;
  wire [(I-1):0]    wid;
  logic              wlast;
  wire              wlast;
  logic              wready;
  wire              wready;
  logic [N-1:0]      wstrb;
  wire [N-1:0]      wstrb;
  logic              wvalid;
  wire              wvalid;
 
 
 
 
 
// --------------------------------------------------------------------
 
// synthesis translate_off
 
  clocking cb_s @(posedge aclk);
 
    input   arid;
 
    input   araddr;
 
    input   arburst;
 
    input   arcache;
 
    input   awid;
 
    input   arlen;
 
    input   arlock;
 
    input   arprot;
 
    input   arqos;
 
    output  arready;
 
    input   arregion;
 
    input   arsize;
 
    input   arvalid;
 
    input   awaddr;
 
    input   awburst;
 
    input   awcache;
 
    input   awlen;
 
    input   awlock;
 
    input   awprot;
 
    input   awqos;
 
    output  awready;
 
    input   awregion;
 
    input   awsize;
 
    input   awvalid;
 
    input   bready;
 
    output  bid;
 
    output  bresp;
 
    output  bvalid;
 
    output  rdata;
 
    output  rid;
 
    output  rlast;
 
    input   rready;
 
    output  rresp;
 
    output  rvalid;
 
    input   wdata;
 
    input   wid;
 
    input   wlast;
 
    output  wready;
 
    input   wstrb;
 
    input   wvalid;
 
    input   aresetn;
 
    input   aclk;
 
  endclocking
 
 
 
 
// --------------------------------------------------------------------
// --------------------------------------------------------------------
//
//
 
  default clocking cb_m @(posedge aclk);
 
    output  arid;
 
    output  araddr;
 
    output  arburst;
 
    output  arcache;
 
    output  awid;
 
    output  arlen;
 
    output  arlock;
 
    output  arprot;
 
    output  arqos;
 
    input   arready;
 
    output  arregion;
 
    output  arsize;
 
    output  arvalid;
 
    output  awaddr;
 
    output  awburst;
 
    output  awcache;
 
    output  awlen;
 
    output  awlock;
 
    output  awprot;
 
    output  awqos;
 
    input   awready;
 
    output  awregion;
 
    output  awsize;
 
    output  awvalid;
 
    output  bready;
 
    input   bid;
 
    input   bresp;
 
    input   bvalid;
 
    input   rdata;
 
    input   rid;
 
    input   rlast;
 
    output  rready;
 
    input   rresp;
 
    input   rvalid;
 
    output  wdata;
 
    output  wid;
 
    output  wlast;
 
    input   wready;
 
    output  wstrb;
 
    output  wvalid;
 
    input   aresetn;
 
    input   aclk;
 
  endclocking
 
// synthesis translate_on
 
// --------------------------------------------------------------------
 
 
endinterface
 
 
 
 
  // --------------------------------------------------------------------
 
  //
 
`ifdef USE_MOD_PORTS
 
  // --------------------------------------------------------------------
 
  //
 
    modport
 
      slave
 
      (
 
// --------------------------------------------------------------------
 
// synthesis translate_off
 
        clocking  cb_s,
 
// synthesis translate_on
 
// --------------------------------------------------------------------
 
        input   arid,
 
        input   araddr,
 
        input   arburst,
 
        input   arcache,
 
        input   awid,
 
        input   arlen,
 
        input   arlock,
 
        input   arprot,
 
        input   arqos,
 
        output  arready,
 
        input   arregion,
 
        input   arsize,
 
        input   arvalid,
 
        input   awaddr,
 
        input   awburst,
 
        input   awcache,
 
        input   awlen,
 
        input   awlock,
 
        input   awprot,
 
        input   awqos,
 
        output  awready,
 
        input   awregion,
 
        input   awsize,
 
        input   awvalid,
 
        input   bready,
 
        output  bid,
 
        output  bresp,
 
        output  bvalid,
 
        output  rdata,
 
        output  rid,
 
        output  rlast,
 
        input   rready,
 
        output  rresp,
 
        output  rvalid,
 
        input   wdata,
 
        input   wid,
 
        input   wlast,
 
        output  wready,
 
        input   wstrb,
 
        input   wvalid,
 
        input   aresetn,
 
        input   aclk
 
      );
 
 
 
 
 
  // --------------------------------------------------------------------
 
  //
 
    modport
 
      master
 
      (
 
// --------------------------------------------------------------------
 
// synthesis translate_off
 
        clocking  cb_m,
 
// synthesis translate_on
 
// --------------------------------------------------------------------
 
        output  arid,
 
        output  araddr,
 
        output  arburst,
 
        output  arcache,
 
        output  awid,
 
        output  arlen,
 
        output  arlock,
 
        output  arprot,
 
        output  arqos,
 
        input   arready,
 
        output  arregion,
 
        output  arsize,
 
        output  arvalid,
 
        output  awaddr,
 
        output  awburst,
 
        output  awcache,
 
        output  awlen,
 
        output  awlock,
 
        output  awprot,
 
        output  awqos,
 
        input   awready,
 
        output  awregion,
 
        output  awsize,
 
        output  awvalid,
 
        output  bready,
 
        input   bid,
 
        input   bresp,
 
        input   bvalid,
 
        input   rdata,
 
        input   rid,
 
        input   rlast,
 
        output  rready,
 
        input   rresp,
 
        input   rvalid,
 
        output  wdata,
 
        output  wlast,
 
        input   wready,
 
        output  wstrb,
 
        output  wvalid,
 
        input   aresetn,
 
        input   aclk
 
      );
 
`endif
 
 
 
 
 
// --------------------------------------------------------------------
 
// synthesis translate_off
 
  task
 
    zero_cycle_delay;
 
 
 
    ##0;
 
 
 
  endtask: zero_cycle_delay
 
// synthesis translate_on
 
// --------------------------------------------------------------------
 
 
 
 
 
// --------------------------------------------------------------------
 
//
 
 
 
endinterface
 
 

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