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[/] [qaz_libs/] [trunk/] [axi4_lib/] [src/] [axi4_m_to_read_fifos.sv] - Diff between revs 31 and 43

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Rev 31 Rev 43
Line 26... Line 26...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
module
module
  axi4_m_to_read_fifos
  axi4_m_to_read_fifos
  #(
  #(
    A     = 32, // address bus width
    A, // address bus width
    N     = 8,  // data bus width in bytes
    N,  // data bus width in bytes
    I     = 1,  // ID width
    I,  // ID width
    R_D   = 32,
    R_D,
    AR_D  = 2,
    AR_D,
    WATERMARK = 0,
    WATERMARK = 0,
    USE_ADVANCED_PROTOCOL = 0
    USE_ADVANCED_PROTOCOL = 0
  )
  )
  (
  (
    axi4_if     axi4_m,
    axi4_if     axi4_m,
Line 181... Line 181...
  wire [R_W-1:0] r_rd_data;
  wire [R_W-1:0] r_rd_data;
  wire [R_W-1:0] r_wr_data;
  wire [R_W-1:0] r_wr_data;
 
 
  assign r_wr_data =
  assign r_wr_data =
    {
    {
      axi4_m.rdata,
 
      axi4_m.rid,
      axi4_m.rid,
 
      axi4_m.rresp,
      axi4_m.rlast,
      axi4_m.rlast,
      axi4_m.rresp
      axi4_m.rdata
    };
    };
 
 
  assign
  assign
    {
    {
      axi4_read_fifo.rdata,
 
      axi4_read_fifo.rid,
      axi4_read_fifo.rid,
 
      axi4_read_fifo.rresp,
      axi4_read_fifo.rlast,
      axi4_read_fifo.rlast,
      axi4_read_fifo.rresp
      axi4_read_fifo.rdata
    } = r_rd_data;
    } = r_rd_data;
 
 
 
 
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  //

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