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[/] [qaz_libs/] [trunk/] [axi4_lite_lib/] [src/] [axi4_lite_register_file.sv] - Diff between revs 29 and 31

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Rev 29 Rev 31
Line 28... Line 28...
module
module
  axi4_lite_register_file
  axi4_lite_register_file
  #(
  #(
    A   = 32,     //  address bus width, must be 32 or greater for axi lite
    A   = 32,     //  address bus width, must be 32 or greater for axi lite
    N   = 8,      //  data bus width in bytes, must be 4 or 8 for axi lite
    N   = 8,      //  data bus width in bytes, must be 4 or 8 for axi lite
    I   = 1       //  ID width
    I   = 1,      //  ID width
 
    MW  = 3       //  mux select width
  )
  )
  (
  (
    axi4_if               axi4_s,
    axi4_if               axi4_s,
    axi4_lite_register_if r_if,
    axi4_lite_register_if r_if,
    input                 aclk,
    input                 aclk,
    input                 aresetn
    input                 aresetn
  );
  );
 
 
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  //
 
  localparam MI = 2 ** MW; //  mux inputs
  localparam LB = (N == 8) ? 3 : 2;
  localparam LB = (N == 8) ? 3 : 2;
  localparam UB = LB + r_if.MW - 1;
  localparam UB = LB + MW - 1;
 
 
 
 
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  //
  wire aw_rd_empty;
  wire aw_rd_empty;
Line 56... Line 58...
  wire b_wr_en = rf_wr_en;
  wire b_wr_en = rf_wr_en;
 
 
  axi4_if #(.A(A), .N(N), .I(I))
  axi4_if #(.A(A), .N(N), .I(I))
    axi4_write_fifo(.*);
    axi4_write_fifo(.*);
 
 
  axi4_to_write_fifos #(.A(A), .N(N), .I(I), .USE_ADVANCED_PROTOCOL(0))
  axi4_s_to_write_fifos #(.A(A), .N(N), .I(I), .USE_ADVANCED_PROTOCOL(0))
    axi4_to_write_fifos_i(.*);
    axi4_s_to_write_fifos_i(.*);
 
 
 
 
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  //
  wire register_select [r_if.MI-1:0];
  wire register_select [MI-1:0];
  genvar j;
  genvar j;
 
 
  generate
  generate
    for(j = 0; j < r_if.MI; j = j + 1)
    for(j = 0; j < MI; j = j + 1)
    begin: decoder_gen
    begin: decoder_gen
      assign register_select[j] = (axi4_write_fifo.awaddr[UB:LB] == j) ? 1 : 0;
      assign register_select[j] = (axi4_write_fifo.awaddr[UB:LB] == j) ? 1 : 0;
 
 
      always_ff @(posedge aclk)
      always_ff @(posedge aclk)
        if(~aresetn)
        if(~aresetn)
Line 90... Line 92...
  wire r_wr_en = rf_rd_en;
  wire r_wr_en = rf_rd_en;
 
 
  axi4_if #(.A(A), .N(N), .I(I))
  axi4_if #(.A(A), .N(N), .I(I))
    axi4_read_fifo(.*);
    axi4_read_fifo(.*);
 
 
  axi4_to_read_fifos #(.A(A), .N(N), .I(I), .USE_ADVANCED_PROTOCOL(0))
  axi4_s_to_read_fifos #(.A(A), .N(N), .I(I), .USE_ADVANCED_PROTOCOL(0))
    axi4_to_read_fifos_i(.*);
    axi4_s_to_read_fifos_i(.*);
 
 
 
 
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  //
  recursive_mux #(.A(r_if.MW), .W(N*8))
  recursive_mux #(.A(MW), .W(N*8))
    recursive_mux_i
    recursive_mux_i
    (
    (
      .select(axi4_read_fifo.araddr[UB:LB]),
      .select(axi4_read_fifo.araddr[UB:LB]),
      .data_in(r_if.register_in),
      .data_in(r_if.register_in),
      .data_out(axi4_read_fifo.rdata)
      .data_out(axi4_read_fifo.rdata)

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