//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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module
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module
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axi4_lite_register_file
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axi4_lite_register_file
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#(
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#(
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A = 32, // address bus width, must be 32 or greater for axi lite
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A = 32, // address bus width, must be 32 or greater for axi lite
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N = 8, // data bus width in bytes, must be 4 or 8 for axi lite
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N = 8, // data bus width in bytes, must be 4 or 8 for axi lite
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I = 1, // ID width
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I = 1, // ID width
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MW = 3 // mux select width
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MW = 3 // mux select width
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)
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)
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(
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(
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axi4_if axi4_s,
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axi4_if axi4_s,
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axi4_lite_register_if r_if,
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axi4_lite_register_if r_if,
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input aclk,
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input aclk,
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input aresetn
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input aresetn
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);
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);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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localparam MI = 2 ** MW; // mux inputs
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localparam MI = 2 ** MW; // mux inputs
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localparam LB = (N == 8) ? 3 : 2;
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localparam LB = (N == 8) ? 3 : 2;
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localparam UB = LB + MW - 1;
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localparam UB = LB + MW - 1;
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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wire aw_rd_empty;
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wire aw_rd_empty;
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wire w_rd_empty;
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wire w_rd_empty;
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wire b_wr_full;
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wire b_wr_full;
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wire rf_wr_en = ~aw_rd_empty & ~w_rd_empty & ~b_wr_full;
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wire rf_wr_en = ~aw_rd_empty & ~w_rd_empty & ~b_wr_full;
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wire aw_rd_en = rf_wr_en;
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wire aw_rd_en = rf_wr_en;
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wire w_rd_en = rf_wr_en;
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wire w_rd_en = rf_wr_en;
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wire b_wr_en = rf_wr_en;
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wire b_wr_en = rf_wr_en;
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axi4_if #(.A(A), .N(N), .I(I))
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axi4_if #(.A(A), .N(N), .I(I))
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axi4_write_fifo(.*);
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axi4_write_fifo(.*);
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axi4_s_to_write_fifos #(.A(A), .N(N), .I(I), .USE_ADVANCED_PROTOCOL(0))
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axi4_s_to_write_fifos #(.A(A), .N(N), .I(I), .USE_ADVANCED_PROTOCOL(0))
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axi4_s_to_write_fifos_i(.*);
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axi4_s_to_write_fifos_i(.*);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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wire register_select [MI-1:0];
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wire register_select [MI-1:0];
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genvar j;
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genvar j;
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generate
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generate
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for(j = 0; j < MI; j = j + 1)
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for(j = 0; j < MI; j = j + 1)
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begin: decoder_gen
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begin: decoder_gen
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assign register_select[j] = (axi4_write_fifo.awaddr[UB:LB] == j) ? 1 : 0;
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assign register_select[j] = (axi4_write_fifo.awaddr[UB:LB] == j) ? 1 : 0;
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assign r_if.wr_en[j] = rf_wr_en & register_select[j];
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always_ff @(posedge aclk)
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always_ff @(posedge aclk)
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if(~aresetn)
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if(~aresetn)
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r_if.register_out[j] <= 0;
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r_if.register_out[j] <= 0;
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else if(rf_wr_en & register_select[j])
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else if(r_if.wr_en[j])
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r_if.register_out[j] <= axi4_write_fifo.wdata;
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r_if.register_out[j] <= axi4_write_fifo.wdata;
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end
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end
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endgenerate
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endgenerate
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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wire ar_rd_empty;
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wire ar_rd_empty;
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wire r_wr_full;
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wire r_wr_full;
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wire rf_rd_en = ~ar_rd_empty & ~r_wr_full;
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wire rf_rd_en = ~ar_rd_empty & ~r_wr_full;
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wire ar_rd_en = rf_rd_en;
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wire ar_rd_en = rf_rd_en;
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wire r_wr_en = rf_rd_en;
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wire r_wr_en = rf_rd_en;
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axi4_if #(.A(A), .N(N), .I(I))
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axi4_if #(.A(A), .N(N), .I(I))
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axi4_read_fifo(.*);
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axi4_read_fifo(.*);
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axi4_s_to_read_fifos #(.A(A), .N(N), .I(I), .USE_ADVANCED_PROTOCOL(0))
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axi4_s_to_read_fifos #(.A(A), .N(N), .I(I), .USE_ADVANCED_PROTOCOL(0))
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axi4_s_to_read_fifos_i(.*);
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axi4_s_to_read_fifos_i(.*);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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recursive_mux #(.A(MW), .W(N*8))
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recursive_mux #(.A(MW), .W(N*8))
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recursive_mux_i
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recursive_mux_i
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(
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(
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.select(axi4_read_fifo.araddr[UB:LB]),
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.select(axi4_read_fifo.araddr[UB:LB]),
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.data_in(r_if.register_in),
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.data_in(r_if.register_in),
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.data_out(axi4_read_fifo.rdata)
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.data_out(axi4_read_fifo.rdata)
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);
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);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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assign axi4_read_fifo.rid = 0;
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assign axi4_read_fifo.rid = 0;
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assign axi4_read_fifo.rlast = 1;
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assign axi4_read_fifo.rlast = 1;
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assign axi4_read_fifo.rresp = 0;
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assign axi4_read_fifo.rresp = 0;
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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assign axi4_write_fifo.bid = 0;
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assign axi4_write_fifo.bid = 0;
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assign axi4_write_fifo.bresp = 0;
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assign axi4_write_fifo.bresp = 0;
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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endmodule
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endmodule
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