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[/] [qaz_libs/] [trunk/] [axi4_lite_lib/] [src/] [axi4_lite_register_if.sv] - Diff between revs 29 and 31

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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
interface
interface
  axi4_lite_register_if
  axi4_lite_register_if
  #(
  #(
    N   = 8,      //  data bus width in bytes, must be 4 or 8 for axi lite
    N   = 8,      //  data bus width in bytes, must be 4 or 8 for axi lite
    MW  = 3,      //  mux select width
    MW  = 3,      //  mux select width
    MI  = 2 ** MW //  mux inputs
    MI  = 2 ** MW //  mux inputs
  )
  )
  (
  (
    input aclk,
    input aclk,
    input aresetn
    input aresetn
  );
  );
  wire  [(N*8)-1:0] register_in   [MI-1:0];
  wire  [(N*8)-1:0] register_in   [MI-1:0];
  reg   [(N*8)-1:0] register_out  [MI-1:0];
  reg   [(N*8)-1:0] register_out  [MI-1:0];
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// synthesis translate_off
// synthesis translate_off
    initial
    initial
      a_data_bus_width: assert((N == 8) | (N == 4)) else $fatal;
      a_data_bus_width: assert((N == 8) | (N == 4)) else $fatal;
 
 
 
 
// synthesis translate_on
// synthesis translate_on
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// --------------------------------------------------------------------
//
//
endinterface
endinterface
 
 

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