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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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module
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module
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axis_mux
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axis_mux
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#(
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#(
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N = 8, // data bus width in bytes
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N, // data bus width in bytes
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I = 1, // TID width
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I = 0, // TID width
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D = 1, // TDEST width
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D = 0, // TDEST width
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U = 1, // TUSER width
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U = 1, // TUSER width
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USE_TSTRB = 0, // set to 1 to enable, 0 to disable
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USE_TSTRB = 0, // set to 1 to enable, 0 to disable
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USE_TKEEP = 0 // set to 1 to enable, 0 to disable
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USE_TKEEP = 0 // set to 1 to enable, 0 to disable
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)
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)
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(
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(
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input mux_select,
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input mux_select,
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axis_if.slave axis_0_in,
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axis_if axis_0_in,
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axis_if.slave axis_1_in,
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axis_if axis_1_in,
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axis_if.master axis_out,
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axis_if axis_out,
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input axis_en,
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input axis_en,
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input aclk,
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input aclk,
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input aresetn
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input aresetn
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);
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);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// synthesis translate_off
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initial
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begin
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a_tid_unsuported: assert(I == 0) else $fatal;
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a_tdest_unsuported: assert(D == 0) else $fatal;
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end
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// synthesis translate_on
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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axis_if #(.N(N), .I(I), .D(D), .U(U))
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axis_if #(.N(N), .I(1), .D(1), .U(U))
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axis_mux_out(.*);
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axis_mux_out(.*);
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assign axis_0_in.tready = mux_select ? 0 : axis_mux_out.tready;
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assign axis_0_in.tready = mux_select ? 0 : axis_mux_out.tready;
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assign axis_1_in.tready = mux_select ? axis_mux_out.tready : 0;
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assign axis_1_in.tready = mux_select ? axis_mux_out.tready : 0;
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