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[/] [qaz_libs/] [trunk/] [axi4_stream_lib/] [src/] [axis_mux.sv] - Diff between revs 31 and 36

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Rev 31 Rev 36
Line 27... Line 27...
 
 
module
module
  axis_mux
  axis_mux
  #(
  #(
    N,              // data bus width in bytes
    N,              // data bus width in bytes
    I = 0,          // TID width
    I = 1,  // TID width
    D = 0,          // TDEST width
    D = 1,  // TDEST width
    U = 1,          // TUSER width
    U = 1,          // TUSER width
    USE_TSTRB = 0,  //  set to 1 to enable, 0 to disable
    USE_TSTRB = 0,  //  set to 1 to enable, 0 to disable
    USE_TKEEP = 0   //  set to 1 to enable, 0 to disable
    USE_TKEEP = 0   //  set to 1 to enable, 0 to disable
  )
  )
  (
  (
    input   mux_select,
    input   select,
    axis_if axis_0_in,
    axis_if axis_in[1:0],
    axis_if axis_1_in,
 
    axis_if axis_out,
    axis_if axis_out,
    input   axis_en,
 
    input   aclk,
    input   aclk,
    input   aresetn
    input   aresetn
  );
  );
 
 
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// synthesis translate_off
 
  initial
 
  begin
 
    a_tid_unsuported:   assert(I == 0) else $fatal;
 
    a_tdest_unsuported: assert(D == 0) else $fatal;
 
  end
 
// synthesis translate_on
 
// --------------------------------------------------------------------
 
 
 
 
 
  // --------------------------------------------------------------------
 
  //
  //
  axis_if #(.N(N), .I(1), .D(1), .U(U))
  axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_mux_out(.*);
    axis_mux_out(.*);
 
 
 
  assign axis_0_in.tready = mux_select ? 0                    : axis_mux_out.tready;
  assign axis_in[0].tready = select ? 0                   : axis_mux_out.tready;
  assign axis_1_in.tready = mux_select ? axis_mux_out.tready  : 0;
  assign axis_in[1].tready = select ? axis_mux_out.tready : 0;
 
 
  assign axis_mux_out.tvalid = mux_select ? axis_1_in.tvalid : axis_0_in.tvalid;
  assign axis_mux_out.tvalid = select ? axis_in[1].tvalid : axis_in[0].tvalid;
  assign axis_mux_out.tdata  = mux_select ? axis_1_in.tdata  : axis_0_in.tdata;
  assign axis_mux_out.tdata  = select ? axis_in[1].tdata  : axis_in[0].tdata;
  assign axis_mux_out.tstrb  = mux_select ? axis_1_in.tstrb  : axis_0_in.tstrb;
  assign axis_mux_out.tstrb  = select ? axis_in[1].tstrb  : axis_in[0].tstrb;
  assign axis_mux_out.tkeep  = mux_select ? axis_1_in.tkeep  : axis_0_in.tkeep;
  assign axis_mux_out.tkeep  = select ? axis_in[1].tkeep  : axis_in[0].tkeep;
  assign axis_mux_out.tlast  = mux_select ? axis_1_in.tlast  : axis_0_in.tlast;
  assign axis_mux_out.tlast  = select ? axis_in[1].tlast  : axis_in[0].tlast;
  assign axis_mux_out.tid    = mux_select ? axis_1_in.tid    : axis_0_in.tid;
  assign axis_mux_out.tid    = select ? axis_in[1].tid    : axis_in[0].tid;
  assign axis_mux_out.tdest  = mux_select ? axis_1_in.tdest  : axis_0_in.tdest;
  assign axis_mux_out.tdest  = select ? axis_in[1].tdest  : axis_in[0].tdest;
  assign axis_mux_out.tuser  = mux_select ? axis_1_in.tuser  : axis_0_in.tuser;
  assign axis_mux_out.tuser  = select ? axis_in[1].tuser  : axis_in[0].tuser;
 
 
 
 
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  //
  axis_register_slice
  axis_register_slice
    #(
    #(
      .N(N),
      .N(N),
      .I(I),
      .I(I),
      .D(D),
      .D(D),
      .U(U),
      .U(U),
      .USE_TSTRB(USE_TSTRB),
      .USE_TSTRB(0),
      .USE_TKEEP(USE_TKEEP)
      .USE_TKEEP(0)
    )
    )
    axis_register_slice_i
    axis_register_slice_i
    (
    (
      .axis_in(axis_mux_out), //  .slave
      .axis_in(axis_mux_out), // slave
      .axis_out(axis_out),    //  .master
      .axis_out(axis_out),    // master
      .*
      .*
    );
    );
 
 
 
 
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  //
 
 
 
 
endmodule
endmodule
 
 
 
 

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