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module
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module
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axis_mux
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axis_mux
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#(
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#(
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N, // data bus width in bytes
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N, // data bus width in bytes
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I = 0, // TID width
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I = 1, // TID width
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D = 0, // TDEST width
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D = 1, // TDEST width
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U = 1, // TUSER width
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U = 1, // TUSER width
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USE_TSTRB = 0, // set to 1 to enable, 0 to disable
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USE_TSTRB = 0, // set to 1 to enable, 0 to disable
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USE_TKEEP = 0 // set to 1 to enable, 0 to disable
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USE_TKEEP = 0 // set to 1 to enable, 0 to disable
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)
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)
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(
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(
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input mux_select,
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input select,
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axis_if axis_0_in,
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axis_if axis_in[1:0],
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axis_if axis_1_in,
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axis_if axis_out,
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axis_if axis_out,
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input axis_en,
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input aclk,
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input aclk,
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input aresetn
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input aresetn
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);
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);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// synthesis translate_off
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initial
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begin
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a_tid_unsuported: assert(I == 0) else $fatal;
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a_tdest_unsuported: assert(D == 0) else $fatal;
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end
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// synthesis translate_on
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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axis_if #(.N(N), .I(1), .D(1), .U(U))
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axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_mux_out(.*);
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axis_mux_out(.*);
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assign axis_0_in.tready = mux_select ? 0 : axis_mux_out.tready;
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assign axis_in[0].tready = select ? 0 : axis_mux_out.tready;
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assign axis_1_in.tready = mux_select ? axis_mux_out.tready : 0;
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assign axis_in[1].tready = select ? axis_mux_out.tready : 0;
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assign axis_mux_out.tvalid = mux_select ? axis_1_in.tvalid : axis_0_in.tvalid;
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assign axis_mux_out.tvalid = select ? axis_in[1].tvalid : axis_in[0].tvalid;
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assign axis_mux_out.tdata = mux_select ? axis_1_in.tdata : axis_0_in.tdata;
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assign axis_mux_out.tdata = select ? axis_in[1].tdata : axis_in[0].tdata;
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assign axis_mux_out.tstrb = mux_select ? axis_1_in.tstrb : axis_0_in.tstrb;
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assign axis_mux_out.tstrb = select ? axis_in[1].tstrb : axis_in[0].tstrb;
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assign axis_mux_out.tkeep = mux_select ? axis_1_in.tkeep : axis_0_in.tkeep;
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assign axis_mux_out.tkeep = select ? axis_in[1].tkeep : axis_in[0].tkeep;
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assign axis_mux_out.tlast = mux_select ? axis_1_in.tlast : axis_0_in.tlast;
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assign axis_mux_out.tlast = select ? axis_in[1].tlast : axis_in[0].tlast;
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assign axis_mux_out.tid = mux_select ? axis_1_in.tid : axis_0_in.tid;
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assign axis_mux_out.tid = select ? axis_in[1].tid : axis_in[0].tid;
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assign axis_mux_out.tdest = mux_select ? axis_1_in.tdest : axis_0_in.tdest;
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assign axis_mux_out.tdest = select ? axis_in[1].tdest : axis_in[0].tdest;
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assign axis_mux_out.tuser = mux_select ? axis_1_in.tuser : axis_0_in.tuser;
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assign axis_mux_out.tuser = select ? axis_in[1].tuser : axis_in[0].tuser;
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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axis_register_slice
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axis_register_slice
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#(
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#(
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.N(N),
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.N(N),
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.I(I),
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.I(I),
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.D(D),
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.D(D),
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.U(U),
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.U(U),
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.USE_TSTRB(USE_TSTRB),
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.USE_TSTRB(0),
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.USE_TKEEP(USE_TKEEP)
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.USE_TKEEP(0)
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)
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)
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axis_register_slice_i
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axis_register_slice_i
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(
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(
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.axis_in(axis_mux_out), // .slave
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.axis_in(axis_mux_out), // slave
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.axis_out(axis_out), // .master
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.axis_out(axis_out), // master
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.*
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.*
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);
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);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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endmodule
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endmodule
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