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[/] [qaz_libs/] [trunk/] [axi4_stream_lib/] [src/] [axis_register_slice.sv] - Diff between revs 28 and 31

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Rev 28 Rev 31
Line 34... Line 34...
    U = 1,          // TUSER width
    U = 1,          // TUSER width
    USE_TSTRB = 0,  //  set to 1 to enable, 0 to disable
    USE_TSTRB = 0,  //  set to 1 to enable, 0 to disable
    USE_TKEEP = 0   //  set to 1 to enable, 0 to disable
    USE_TKEEP = 0   //  set to 1 to enable, 0 to disable
  )
  )
  (
  (
    input           axis_en,
    axis_if axis_in,
    axis_if.slave   axis_in,
    axis_if axis_out,
    axis_if.master  axis_out,
 
    input           aclk,
    input           aclk,
    input           aresetn
    input           aresetn
  );
  );
 
 
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
// synthesis translate_off
  localparam W = (N * 8) + (N * USE_TSTRB) + (N * USE_TKEEP) + I + D + U + 1;
  initial
 
  begin
 
    a_tid_unsuported:   assert(I == 0) else $fatal;
 
    a_tdest_unsuported: assert(D == 0) else $fatal;
 
  end
 
// synthesis translate_on
 
// --------------------------------------------------------------------
 
 
  fifo_write_if #(.W(W)) fifo_sink(aclk, ~aresetn);
 
  fifo_read_if  #(.W(W)) fifo_source(aclk, ~aresetn);
 
 
 
  tiny_sync_fifo #(.W(W))
  // --------------------------------------------------------------------
    tiny_sync_fifo_i(.source(fifo_sink.fifo), .sink(fifo_source.fifo));
  //
 
  localparam W = (N * 8) + (N * USE_TSTRB) + (N * USE_TKEEP) + I + D + U + 1;
 
 
 
 
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  //
  wire data_to_axis_fsm_error;
  wire          wr_full;
 
  wire [W-1:0]  wr_data;
 
  wire          wr_en;
 
 
 
  wire          rd_empty;
 
  wire [W-1:0]  rd_data;
 
  wire          rd_en;
 
 
  data_to_axis_fsm
  tiny_sync_fifo #(.W(W))
    data_to_axis_fsm_i
    tiny_sync_fifo_i(.clk(aclk), .reset(~aresetn), .*);
    (
 
      .axis_tvalid(axis_out.tvalid),
 
      .axis_tready(axis_out.tready),
 
      .fifo_empty(fifo_source.empty),
 
      .fifo_rd_en(fifo_source.rd_en),
 
      .fifo_watermark(1'b1),
 
      .*
 
    );
 
 
 
 
 
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  //
  generate
  generate
    begin: assign_gen
    begin: assign_gen
 
 
      if(USE_TSTRB & USE_TKEEP)
      if(USE_TSTRB & USE_TKEEP)
      begin
      begin
        assign fifo_sink.wr_data =
        assign wr_data =
          {
          {
            axis_in.tdata,
            axis_in.tdata,
            axis_in.tlast,
            axis_in.tlast,
            axis_in.tuser,
            axis_in.tuser,
            axis_in.tstrb,
            axis_in.tstrb,
Line 90... Line 91...
            axis_out.tdata,
            axis_out.tdata,
            axis_out.tlast,
            axis_out.tlast,
            axis_out.tuser,
            axis_out.tuser,
            axis_out.tstrb,
            axis_out.tstrb,
            axis_out.tkeep
            axis_out.tkeep
          } = fifo_source.rd_data;
          } = rd_data;
      end
      end
      else if(USE_TSTRB)
      else if(USE_TSTRB)
      begin
      begin
        assign fifo_sink.wr_data =
        assign wr_data =
          {
          {
            axis_in.tdata,
            axis_in.tdata,
            axis_in.tlast,
            axis_in.tlast,
            axis_in.tuser,
            axis_in.tuser,
            axis_in.tstrb
            axis_in.tstrb
Line 107... Line 108...
          {
          {
            axis_out.tdata,
            axis_out.tdata,
            axis_out.tlast,
            axis_out.tlast,
            axis_out.tuser,
            axis_out.tuser,
            axis_out.tstrb
            axis_out.tstrb
          } = fifo_source.rd_data;
          } = rd_data;
      end
      end
      else if(USE_TKEEP)
      else if(USE_TKEEP)
      begin
      begin
        assign fifo_sink.wr_data =
        assign wr_data =
          {
          {
            axis_in.tdata,
            axis_in.tdata,
            axis_in.tlast,
            axis_in.tlast,
            axis_in.tuser,
            axis_in.tuser,
            axis_in.tkeep
            axis_in.tkeep
Line 124... Line 125...
          {
          {
            axis_out.tdata,
            axis_out.tdata,
            axis_out.tlast,
            axis_out.tlast,
            axis_out.tuser,
            axis_out.tuser,
            axis_out.tkeep
            axis_out.tkeep
          } = fifo_source.rd_data;
          } = rd_data;
      end
      end
      else
      else
      begin
      begin
        assign fifo_sink.wr_data =
        assign wr_data =
          {
          {
            axis_in.tdata,
            axis_in.tdata,
            axis_in.tlast,
            axis_in.tlast,
            axis_in.tuser
            axis_in.tuser
          };
          };
        assign
        assign
          {
          {
            axis_out.tdata,
            axis_out.tdata,
            axis_out.tlast,
            axis_out.tlast,
            axis_out.tuser
            axis_out.tuser
          } = fifo_source.rd_data;
          } = rd_data;
      end
      end
 
 
    end
    end
  endgenerate
  endgenerate
 
 
 
 
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  //
  assign axis_in.tready   = ~fifo_sink.full;
  assign axis_in.tready   = ~wr_full;
  assign fifo_sink.wr_en  = axis_in.tvalid & ~fifo_sink.full;
  assign wr_en            = axis_in.tvalid & ~wr_full;
 
  assign axis_out.tvalid  = ~rd_empty;
 
  assign rd_en            = axis_out.tready & ~rd_empty;
 
 
 
 
 
// --------------------------------------------------------------------
 
//
endmodule
endmodule
 
 

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