OpenCores
URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

[/] [qaz_libs/] [trunk/] [axi4_stream_lib/] [src/] [axis_register_slice.sv] - Diff between revs 31 and 36

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 31 Rev 36
Line 26... Line 26...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
module
module
  axis_register_slice
  axis_register_slice
  #(
  #(
    N = 8,          // data bus width in bytes
    N,              // data bus width in bytes
    I = 0,          // TID width
    I = 1,          // TID width
    D = 0,          // TDEST width
    D = 1,          // TDEST width
    U = 1,          // TUSER width
    U = 1,          // TUSER width
    USE_TSTRB = 0,  //  set to 1 to enable, 0 to disable
    USE_TSTRB = 0,  //  set to 1 to enable, 0 to disable
    USE_TKEEP = 0   //  set to 1 to enable, 0 to disable
    USE_TKEEP = 0   //  set to 1 to enable, 0 to disable
  )
  )
  (
  (
Line 41... Line 41...
    input   aclk,
    input   aclk,
    input   aresetn
    input   aresetn
  );
  );
 
 
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// synthesis translate_off
 
  initial
 
  begin
 
    a_tid_unsuported:   assert(I == 0) else $fatal;
 
    a_tdest_unsuported: assert(D == 0) else $fatal;
 
  end
 
// synthesis translate_on
 
// --------------------------------------------------------------------
 
 
 
 
 
  // --------------------------------------------------------------------
 
  //
  //
  localparam W = (N * 8) + (N * USE_TSTRB) + (N * USE_TKEEP) + I + D + U + 1;
  localparam W = (N * 8) + (N * USE_TSTRB) + (N * USE_TKEEP) + I + D + U + 1;
 
 
 
 
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
Line 66... Line 55...
 
 
  wire          rd_empty;
  wire          rd_empty;
  wire [W-1:0]  rd_data;
  wire [W-1:0]  rd_data;
  wire          rd_en;
  wire          rd_en;
 
 
  tiny_sync_fifo #(.W(W))
  defparam tiny_sync_fifo_i.W=W; // why are needed these for recursive modules?
 
  tiny_sync_fifo
 
  // tiny_sync_fifo #(W)
    tiny_sync_fifo_i(.clk(aclk), .reset(~aresetn), .*);
    tiny_sync_fifo_i(.clk(aclk), .reset(~aresetn), .*);
 
 
 
 
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  //

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.