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[/] [qaz_libs/] [trunk/] [axi4_stream_lib/] [src/] [axis_synchronizer.sv] - Diff between revs 31 and 38

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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2016 Authors and OPENCORES.ORG                 ////
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//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
module
module
  axis_synchronizer
  axis_synchronizer
  #(
  #(
    N = 8,          // data bus width in bytes
    N,              // data bus width in bytes
    I = 0,          // TID width
    I = 1,          // TID width
    D = 0,          // TDEST width
    D = 1,          // TDEST width
    U = 1,          // TUSER width
    U = 1,          // TUSER width
    USE_TSTRB = 0,  //  set to 1 to enable, 0 to disable
    USE_TSTRB = 0,  //  set to 1 to enable, 0 to disable
    USE_TKEEP = 0   //  set to 1 to enable, 0 to disable
    USE_TKEEP = 0,  //  set to 1 to enable, 0 to disable
 
    FD
  )
  )
  (
  (
    axis_if axis_in,
    axis_if axis_in,
    axis_if axis_out,
    axis_if axis_out,
    input   wr_clk,
    input   aclk_in,
    input   wr_reset,
    input   aresetn_in,
    input   aclk,
    input   aclk_out,
    input   aresetn
    input   aresetn_out
  );
  );
 
 
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// synthesis translate_off
 
  initial
 
  begin
 
    a_tid_unsuported:   assert(I == 0) else $fatal;
 
    a_tdest_unsuported: assert(D == 0) else $fatal;
 
  end
 
// synthesis translate_on
 
// --------------------------------------------------------------------
 
 
 
 
 
  // --------------------------------------------------------------------
 
  //
  //
  localparam W = (N * 8) + (N * USE_TSTRB) + (N * USE_TKEEP) + I + D + U + 1;
  localparam W = (N * 8) + (N * USE_TSTRB) + (N * USE_TKEEP) + I + D + U + 1;
 
 
 
 
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
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  wire          rd_empty;
  wire          rd_empty;
  wire [W-1:0]  rd_data;
  wire [W-1:0]  rd_data;
  wire          rd_en;
  wire          rd_en;
 
 
  tiny_async_fifo #(.W(W))
  defparam async_fifo_i.W=W; // why are these needed for recursive modules?
    tiny_async_fifo_i(.rd_clk(aclk), .rd_reset(~aresetn), .*);
  defparam async_fifo_i.D=FD;
 
  async_fifo
 
  // async_fifo #(.W(W), .D(FD))
 
    async_fifo_i
 
    (
 
      .wr_clk(aclk_in),
 
      .wr_reset(~aresetn_in),
 
      .rd_clk(aclk_out),
 
      .rd_reset(~aresetn_out),
 
      .*
 
    );
 
 
 
 
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  //
  generate
  defparam axis_map_fifo_i.N=N; // why are these needed for recursive modules?
    begin: assign_gen
  defparam axis_map_fifo_i.I=I;
      if(USE_TSTRB & USE_TKEEP)
  defparam axis_map_fifo_i.D=D;
      begin
  defparam axis_map_fifo_i.U=U;
        assign wr_data =
  defparam axis_map_fifo_i.USE_TSTRB=USE_TSTRB;
          {
  defparam axis_map_fifo_i.USE_TKEEP=USE_TKEEP;
            axis_in.tdata,
  defparam axis_map_fifo_i.W=W;
            axis_in.tlast,
  axis_map_fifo
            axis_in.tuser,
    // #(
            axis_in.tstrb,
      // .N(N),
            axis_in.tkeep
      // .I(I),
          };
      // .D(D),
        assign
      // .U(U),
          {
      // .USE_TSTRB(USE_TSTRB),
            axis_out.tdata,
      // .USE_TKEEP(USE_TKEEP),
            axis_out.tlast,
      // .W(W)
            axis_out.tuser,
    // )
            axis_out.tstrb,
    axis_map_fifo_i(.*);
            axis_out.tkeep
 
          } = rd_data;
 
      end
 
      else if(USE_TSTRB)
 
      begin
 
        assign wr_data =
 
          {
 
            axis_in.tdata,
 
            axis_in.tlast,
 
            axis_in.tuser,
 
            axis_in.tstrb
 
          };
 
        assign
 
          {
 
            axis_out.tdata,
 
            axis_out.tlast,
 
            axis_out.tuser,
 
            axis_out.tstrb
 
          } = rd_data;
 
      end
 
      else if(USE_TKEEP)
 
      begin
 
        assign wr_data =
 
          {
 
            axis_in.tdata,
 
            axis_in.tlast,
 
            axis_in.tuser,
 
            axis_in.tkeep
 
          };
 
        assign
 
          {
 
            axis_out.tdata,
 
            axis_out.tlast,
 
            axis_out.tuser,
 
            axis_out.tkeep
 
          } = rd_data;
 
      end
 
      else
 
      begin
 
        assign wr_data =
 
          {
 
            axis_in.tdata,
 
            axis_in.tlast,
 
            axis_in.tuser
 
          };
 
        assign
 
          {
 
            axis_out.tdata,
 
            axis_out.tlast,
 
            axis_out.tuser
 
          } = rd_data;
 
      end
 
    end
 
  endgenerate
 
 
 
 
 
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
  //
  assign axis_in.tready   = ~wr_full;
  assign axis_in.tready   = ~wr_full;
  assign wr_en            = axis_in.tvalid & axis_in.tready;
  assign wr_en            = axis_in.tvalid & ~wr_full;
  assign axis_out.tvalid  = ~rd_empty;
  assign axis_out.tvalid  = ~rd_empty;
  assign rd_en            = axis_out.tvalid & axis_out.tready;
  assign rd_en            = axis_out.tready & ~rd_empty;
 
 
 
 
// --------------------------------------------------------------------
// --------------------------------------------------------------------
//
//
endmodule
endmodule

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