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[/] [qaz_libs/] [trunk/] [basal/] [src/] [FIFOs/] [sync_fifo.sv] - Diff between revs 38 and 50

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Rev 38 Rev 50
Line 23... Line 23...
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
 
 
module
module
  sync_fifo
  sync_fifo
  #(
  #(
    W = 8,
    W = 8,
    D = 16,
    D = 16,
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  )
  )
  (
  (
    output            wr_full,
    output            wr_full,
    input   [W-1:0]   wr_data,
    input   [W-1:0]   wr_data,
    input             wr_en,
    input             wr_en,
 
 
    output            rd_empty,
    output            rd_empty,
    output  [W-1:0]   rd_data,
    output  [W-1:0]   rd_data,
    input             rd_en,
    input             rd_en,
 
 
    output  [UB:0]    count,
    output  [UB:0]    count,
    input             clk,
    input             clk,
    input             reset
    input             reset
  );
  );
 
 
  // --------------------------------------------------------------------
  // --------------------------------------------------------------------
  //
 
  generate
  generate
    begin: fifo_gen
    begin: fifo_gen
      if(D == 2)
      if(D == 2)
      begin
      begin
        assign count = 0;
        reg [UB:0] count_r;
 
        assign count = count_r;
 
 
 
        always_comb
 
          case({wr_full, rd_empty})
 
            2'b0_0: count_r = 1;
 
            2'b0_1: count_r = 0;
 
            2'b1_0: count_r = 2;
 
            2'b1_1: count_r = 'x; // should never happen
 
          endcase
 
 
        tiny_sync_fifo #(.W(W))
        tiny_sync_fifo #(.W(W))
          tiny_sync_fifo_i(.*);
          tiny_sync_fifo_i(.*);
      end
      end
      else
      else
      begin
      begin
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           );
           );
      end
      end
    end
    end
  endgenerate
  endgenerate
 
 
 
 
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// synthesis translate_off
// synthesis translate_off
  always_ff @(posedge clk)
  always_ff @(posedge clk)
    if(wr_en & wr_full)
    if(wr_en & wr_full)
      $stop;
      $stop;
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    if(rd_en & rd_empty)
    if(rd_en & rd_empty)
      $stop;
      $stop;
// synthesis translate_on
// synthesis translate_on
// --------------------------------------------------------------------
// --------------------------------------------------------------------
 
 
 
 
// --------------------------------------------------------------------
// --------------------------------------------------------------------
//
 
endmodule
endmodule
 
 
 
 

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