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[/] [qaz_libs/] [trunk/] [scripts/] [sim_procs.do] - Diff between revs 23 and 31

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Rev 23 Rev 31
Line 26... Line 26...
# //////////////////////////////////////////////////////////////////////
# //////////////////////////////////////////////////////////////////////
 
 
 
 
# ------------------------------------
# ------------------------------------
#
#
 
proc sim_compile_lib {lib target} {
 
 
 
  global env
 
 
 
  echo "INFO: compiling $target rtl"
 
 
 
  foreach filename [glob -nocomplain -directory ${lib}/sim/libs/${target}_verilog/ *.f] {
 
    echo "INFO: compiling $filename"
 
    vlog -f $filename
 
  }
 
 
 
  foreach filename [glob -nocomplain -directory ${lib}/sim/libs/${target}_VHDL/ *.f] {
 
    echo "INFO: compiling $filename"
 
    vcom -explicit -f $filename
 
  }
 
}
 
 
 
 
 
# ------------------------------------
 
#
proc sim_compile_all { target } {
proc sim_compile_all { target } {
 
 
  global env
  global env
 
 
  echo "INFO: compiling $target rtl"
  echo "INFO: compiling $target rtl"

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