////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: testb.h
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// Filename: testb.h
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//
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//
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// Project: Wishbone Controlled Quad SPI Flash Controller
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// Project: A Set of Wishbone Controlled SPI Flash Controllers
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//
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//
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// Purpose: A wrapper for a common interface to a clocked FPGA core
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// Purpose: A wrapper for a common interface to a clocked FPGA core
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// begin exercised in Verilator.
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// begin exercised in Verilator.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015,2017, Gisselquist Technology, LLC
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// Copyright (C) 2015,2017-2018, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This file is part of the set of Wishbone controlled SPI flash controllers
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// modify it under the terms of the GNU General Public License as published
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// project
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// by the Free Software Foundation, either version 3 of the License, or (at
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//
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// your option) any later version.
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// The Wishbone SPI flash controller project is free software (firmware):
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//
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// you can redistribute it and/or modify it under the terms of the GNU Lesser
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// General Public License as published by the Free Software Foundation, either
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// version 3 of the License, or (at your option) any later version.
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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//
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// for more details.
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// The Wishbone SPI flash controller project is distributed in the hope
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//
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// that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
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// You should have received a copy of the GNU General Public License along
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// warranty of MERCHANTIBILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// GNU Lesser General Public License for more details.
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// target there if the PDF file isn't present.) If not, see
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this program. (It's in the $(ROOT)/doc directory. Run make
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// with no target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: LGPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/lgpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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#ifndef TESTB_H
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#ifndef TESTB_H
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#define TESTB_H
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#define TESTB_H
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#include <stdio.h>
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#include <stdio.h>
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#include <stdint.h>
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#include <stdint.h>
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#include <verilated_vcd_c.h>
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#include <verilated_vcd_c.h>
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#define TBASSERT(TB,A) do { if (!(A)) { (TB).closetrace(); } assert(A); } while(0);
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#define TBASSERT(TB,A) do { if (!(A)) { (TB).closetrace(); } assert(A); } while(0);
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template <class VA> class TESTB {
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template <class VA> class TESTB {
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public:
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public:
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VA *m_core;
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VA *m_core;
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VerilatedVcdC* m_trace;
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VerilatedVcdC* m_trace;
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unsigned long m_tickcount;
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unsigned long m_tickcount;
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TESTB(void) : m_trace(NULL), m_tickcount(0l) {
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TESTB(void) : m_trace(NULL), m_tickcount(0l) {
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m_core = new VA;
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m_core = new VA;
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Verilated::traceEverOn(true);
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Verilated::traceEverOn(true);
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m_core->i_clk = 0;
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m_core->i_clk = 0;
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eval(); // Get our initial values set properly.
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eval(); // Get our initial values set properly.
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}
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}
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virtual ~TESTB(void) {
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virtual ~TESTB(void) {
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if (m_trace) m_trace->close();
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if (m_trace) m_trace->close();
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delete m_core;
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delete m_core;
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m_core = NULL;
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m_core = NULL;
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}
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}
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virtual void opentrace(const char *vcdname) {
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virtual void opentrace(const char *vcdname) {
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if (!m_trace) {
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if (!m_trace) {
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m_trace = new VerilatedVcdC;
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m_trace = new VerilatedVcdC;
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m_core->trace(m_trace, 99);
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m_core->trace(m_trace, 99);
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m_trace->open(vcdname);
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m_trace->open(vcdname);
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}
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}
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}
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}
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virtual void closetrace(void) {
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virtual void closetrace(void) {
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if (m_trace) {
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if (m_trace) {
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m_trace->close();
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m_trace->close();
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m_trace = NULL;
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m_trace = NULL;
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}
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}
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}
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}
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virtual void eval(void) {
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virtual void eval(void) {
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m_core->eval();
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m_core->eval();
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}
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}
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virtual void tick(void) {
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virtual void tick(void) {
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m_tickcount++;
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m_tickcount++;
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// Make sure we have our evaluations straight before the top
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// Make sure we have our evaluations straight before the top
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// of the clock. This is necessary since some of the
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// of the clock. This is necessary since some of the
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// connection modules may have made changes, for which some
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// connection modules may have made changes, for which some
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// logic depends. This forces that logic to be recalculated
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// logic depends. This forces that logic to be recalculated
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// before the top of the clock.
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// before the top of the clock.
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eval();
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eval();
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if (m_trace) m_trace->dump(10*m_tickcount-2);
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if (m_trace) m_trace->dump(10*m_tickcount-2);
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m_core->i_clk = 1;
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m_core->i_clk = 1;
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eval();
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eval();
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if (m_trace) m_trace->dump(10*m_tickcount);
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if (m_trace) m_trace->dump(10*m_tickcount);
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m_core->i_clk = 0;
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m_core->i_clk = 0;
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eval();
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eval();
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if (m_trace) {
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if (m_trace) {
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m_trace->dump(10*m_tickcount+5);
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m_trace->dump(10*m_tickcount+5);
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m_trace->flush();
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m_trace->flush();
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}
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}
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}
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}
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virtual void reset(void) {
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virtual void reset(void) {
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}
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}
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};
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};
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#endif
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#endif
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