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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: llqspi.v
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// Filename: lleqspi.v
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//
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//
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// Project: Wishbone Controlled Quad SPI Flash Controller
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// Project: Wishbone Controlled Quad SPI Flash Controller
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//
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//
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// Purpose: Reads/writes a word (user selectable number of bytes) of data
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// Purpose: Reads/writes a word (user selectable number of bytes) of data
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// to/from a Quad SPI port. The port is understood to be
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// to/from a Quad SPI port. The port is understood to be
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Line 68... |
input [1:0] i_len; // 0=>8bits, 1=>16 bits, 2=>24 bits, 3=>32 bits
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input [1:0] i_len; // 0=>8bits, 1=>16 bits, 2=>24 bits, 3=>32 bits
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input i_spd; // 0 -> normal QPI, 1 -> QSPI
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input i_spd; // 0 -> normal QPI, 1 -> QSPI
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input i_dir; // 0 -> read, 1 -> write to SPI
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input i_dir; // 0 -> read, 1 -> write to SPI
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input i_recycle; // 0 = 20ns, 1 = 50ns
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input i_recycle; // 0 = 20ns, 1 = 50ns
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output reg [31:0] o_word;
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output reg [31:0] o_word;
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output wire o_valid;
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output reg o_valid;
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output reg o_busy;
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output reg o_busy;
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// Interface with the QSPI lines
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// Interface with the QSPI lines
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output reg o_sck;
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output reg o_sck;
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output reg o_cs_n;
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output reg o_cs_n;
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output reg [1:0] o_mod;
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output reg [1:0] o_mod;
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Line 81... |
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// output wire [22:0] o_dbg;
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// output wire [22:0] o_dbg;
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// assign o_dbg = { state, spi_len,
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// assign o_dbg = { state, spi_len,
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// o_busy, o_valid, o_cs_n, o_sck, o_mod, o_dat, i_dat };
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// o_busy, o_valid, o_cs_n, o_sck, o_mod, o_dat, i_dat };
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// Timing:
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//
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// Tick Clk BSY/WR CS_n BIT/MO STATE
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// 0 1 0/0 1 -
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// 1 1 0/1 1 -
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// 2 1 1/0 0 - QSPI_START
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// 3 0 1/0 0 - QSPI_START
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// 4 0 1/0 0 0 QSPI_BITS
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// 5 1 1/0 0 0 QSPI_BITS
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// 6 0 1/0 0 1 QSPI_BITS
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// 7 1 1/0 0 1 QSPI_BITS
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// 8 0 1/0 0 2 QSPI_BITS
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// 9 1 1/0 0 2 QSPI_BITS
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// 10 0 1/0 0 3 QSPI_BITS
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// 11 1 1/0 0 3 QSPI_BITS
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// 12 0 1/0 0 4 QSPI_BITS
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// 13 1 1/0 0 4 QSPI_BITS
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// 14 0 1/0 0 5 QSPI_BITS
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// 15 1 1/0 0 5 QSPI_BITS
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// 16 0 1/0 0 6 QSPI_BITS
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// 17 1 1/1 0 6 QSPI_BITS
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// 18 0 1/1 0 7 QSPI_READY
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// 19 1 0/1 0 7 QSPI_READY
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// 20 0 1/0/V 0 8 QSPI_BITS
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// 21 1 1/0 0 8 QSPI_BITS
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// 22 0 1/0 0 9 QSPI_BITS
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// 23 1 1/0 0 9 QSPI_BITS
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// 24 0 1/0 0 10 QSPI_BITS
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// 25 1 1/0 0 10 QSPI_BITS
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// 26 0 1/0 0 11 QSPI_BITS
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// 27 1 1/0 0 11 QSPI_BITS
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// 28 0 1/0 0 12 QSPI_BITS
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// 29 1 1/0 0 12 QSPI_BITS
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// 30 0 1/0 0 13 QSPI_BITS
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// 31 1 1/0 0 13 QSPI_BITS
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// 32 0 1/0 0 14 QSPI_BITS
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// 33 1 1/0 0 14 QSPI_BITS
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// 34 0 1/0 0 15 QSPI_READY
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// 35 1 1/0 0 15 QSPI_READY
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// 36 1 1/0/V 0 - QSPI_STOP
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// 37 1 1/0 0 - QSPI_STOPB
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// 38 1 1/0 1 - QSPI_IDLE
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// 39 1 0/0 1 -
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// Now, let's switch from single bit to quad mode
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// 40 1 0/0 1 - QSPI_IDLE
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// 41 1 0/1 1 - QSPI_IDLE
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// 42 1 1/0 0 - QSPI_START
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// 43 0 1/0 0 - QSPI_START
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// 44 0 1/0 0 0 QSPI_BITS
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// 45 1 1/0 0 0 QSPI_BITS
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// 46 0 1/0 0 1 QSPI_BITS
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// 47 1 1/0 0 1 QSPI_BITS
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// 48 0 1/0 0 2 QSPI_BITS
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// 49 1 1/0 0 2 QSPI_BITS
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// 50 0 1/0 0 3 QSPI_BITS
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// 51 1 1/0 0 3 QSPI_BITS
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// 52 0 1/0 0 4 QSPI_BITS
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// 53 1 1/0 0 4 QSPI_BITS
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// 54 0 1/0 0 5 QSPI_BITS
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// 55 1 1/0 0 5 QSPI_BITS
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// 56 0 1/0 0 6 QSPI_BITS
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// 57 1 1/1/QR 0 6 QSPI_BITS
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// 58 0 1/1/QR 0 7 QSPI_READY
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// 59 1 0/1/QR 0 7 QSPI_READY
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// 60 0 1/0/?/V 0 8-11 QSPI_BITS
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// 61 1 1/0/? 0 8-11 QSPI_BITS
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// 62 0 1/0/? 0 12-15 QSPI_BITS
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// 63 1 1/0/? 0 12-15 QSPI_BITS
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// 64 1 1/0/?/V 0 - QSPI_STOP
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// 65 1 1/0/? 0 - QSPI_STOPB
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// 66 1 1/0/? 1 - QSPI_IDLE
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// 67 1 0/0 1 - QSPI_IDLE
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// Now let's try something entirely in Quad read mode, from the
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// beginning
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// 68 1 0/1/QR 1 - QSPI_IDLE
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// 69 1 1/0 0 - QSPI_START
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// 70 0 1/0 0 - QSPI_START
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// 71 0 1/0 0 0-3 QSPI_BITS
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// 72 1 1/0 0 0-3 QSPI_BITS
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// 73 0 1/1/QR 0 4-7 QSPI_BITS
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// 74 1 0/1/QR 0 4-7 QSPI_BITS
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// 75 0 1/?/?/V 0 8-11 QSPI_BITS
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// 76 1 1/?/? 0 8-11 QSPI_BITS
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// 77 0 1/1/QR 0 12-15 QSPI_BITS
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// 78 1 0/1/QR 0 12-15 QSPI_BITS
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// 79 0 1/?/?/V 0 16-19 QSPI_BITS
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// 80 1 1/0 0 16-19 QSPI_BITS
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// 81 0 1/0 0 20-23 QSPI_BITS
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// 82 1 1/0 0 20-23 QSPI_BITS
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// 83 1 1/0/V 0 - QSPI_STOP
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// 84 1 1/0 0 - QSPI_STOPB
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// 85 1 1/0 1 - QSPI_IDLE
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// 86 1 0/0 1 - QSPI_IDLE
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wire i_miso;
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wire i_miso;
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assign i_miso = i_dat[1];
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assign i_miso = i_dat[1];
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// These are used in creating a delayed input.
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// These are used in creating a delayed input.
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reg rd_input, rd_spd, rd_valid;
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reg rd_input, rd_spd, rd_valid;
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o_dat <= 4'hd;
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o_dat <= 4'hd;
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end
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end
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*/
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*/
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end
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end
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`define EXTRA_DELAY
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wire rd_input_N, rd_valid_N, r_spd_N;
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`ifdef EXTRA_DELAY
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reg [2:0] rd_input_p, rd_valid_p, r_spd_p;
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always @(posedge i_clk)
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rd_input_p <= { rd_input_p[1:0], rd_input };
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always @(posedge i_clk)
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rd_valid_p <= { rd_valid_p[1:0], rd_valid };
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always @(posedge i_clk)
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r_spd_p <= { r_spd_p[1:0], r_spd };
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assign rd_input_N = rd_input_p[2];
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assign rd_valid_N = rd_valid_p[2];
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assign r_spd_N = r_spd_p[2];
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`else
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assign rd_input_N = rd_input;
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assign rd_valid_N = rd_valid;
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assign r_spd_N = rd_spd;
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`endif
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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if ((state == `EQSPI_IDLE)||(rd_valid))
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// if ((state == `EQSPI_IDLE)||(rd_valid_N))
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if (o_valid)
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r_input <= 31'h00;
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r_input <= 31'h00;
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else if ((rd_input)&&(r_spd))
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if ((rd_input_N)&&(r_spd_N))
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r_input <= { r_input[26:0], i_dat };
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r_input <= { r_input[26:0], i_dat };
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else if (rd_input)
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else if (rd_input_N)
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r_input <= { r_input[29:0], i_miso };
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r_input <= { r_input[29:0], i_miso };
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if ((rd_valid)&&(r_spd))
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if ((rd_valid_N)&&(r_spd_N))
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o_word <= { r_input[27:0], i_dat };
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o_word <= { r_input[27:0], i_dat };
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else if (rd_valid)
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else if (rd_valid_N)
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o_word <= { r_input[30:0], i_miso };
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o_word <= { r_input[30:0], i_miso };
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o_valid <= rd_valid_N;
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end
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end
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assign o_valid = rd_valid;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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