///////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: lleqspi.v
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// Filename: lleqspi.v
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//
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//
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// Project: Wishbone Controlled Quad SPI Flash Controller
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// Project: Wishbone Controlled Quad SPI Flash Controller
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//
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//
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// Purpose: Reads/writes a word (user selectable number of bytes) of data
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// Purpose: Reads/writes a word (user selectable number of bytes) of data
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// to/from a Quad SPI port. The port is understood to be
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// to/from a Quad SPI port. The port is understood to be
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// a normal SPI port unless the driver requests four bit mode.
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// a normal SPI port unless the driver requests four bit mode.
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// When not in use, unlike our previous SPI work, no bits will
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// When not in use, unlike our previous SPI work, no bits will
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// toggle.
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// toggle.
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//
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//
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// Creator: Dan Gisselquist
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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`define EQSPI_IDLE 3'h0
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`define EQSPI_IDLE 3'h0
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`define EQSPI_START 3'h1
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`define EQSPI_START 3'h1
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`define EQSPI_BITS 3'h2
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`define EQSPI_BITS 3'h2
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`define EQSPI_READY 3'h3
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`define EQSPI_READY 3'h3
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`define EQSPI_HOLDING 3'h4
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`define EQSPI_HOLDING 3'h4
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`define EQSPI_STOP 3'h5
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`define EQSPI_STOP 3'h5
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`define EQSPI_STOP_B 3'h6
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`define EQSPI_STOP_B 3'h6
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`define EQSPI_RECYCLE 3'h7
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`define EQSPI_RECYCLE 3'h7
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// Modes
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// Modes
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`define EQSPI_MOD_SPI 2'b00
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`define EQSPI_MOD_SPI 2'b00
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`define EQSPI_MOD_QOUT 2'b10 // Write
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`define EQSPI_MOD_QOUT 2'b10 // Write
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`define EQSPI_MOD_QIN 2'b11 // Read
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`define EQSPI_MOD_QIN 2'b11 // Read
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module lleqspi(i_clk,
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module lleqspi(i_clk,
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// Module interface
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// Module interface
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i_wr, i_hold, i_word, i_len, i_spd, i_dir, i_recycle,
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i_wr, i_hold, i_word, i_len, i_spd, i_dir, i_recycle,
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o_word, o_valid, o_busy,
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o_word, o_valid, o_busy,
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// QSPI interface
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// QSPI interface
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o_sck, o_cs_n, o_mod, o_dat, i_dat);
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o_sck, o_cs_n, o_mod, o_dat, i_dat);
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input i_clk;
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input i_clk;
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// Chip interface
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// Chip interface
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// Can send info
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// Can send info
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// i_dir = 1, i_spd = 0, i_hold = 0, i_wr = 1,
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// i_dir = 1, i_spd = 0, i_hold = 0, i_wr = 1,
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// i_word = { 1'b0, 32'info to send },
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// i_word = { 1'b0, 32'info to send },
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// i_len = # of bytes in word-1
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// i_len = # of bytes in word-1
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input i_wr, i_hold;
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input i_wr, i_hold;
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input [31:0] i_word;
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input [31:0] i_word;
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input [1:0] i_len; // 0=>8bits, 1=>16 bits, 2=>24 bits, 3=>32 bits
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input [1:0] i_len; // 0=>8bits, 1=>16 bits, 2=>24 bits, 3=>32 bits
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input i_spd; // 0 -> normal QPI, 1 -> QSPI
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input i_spd; // 0 -> normal QPI, 1 -> QSPI
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input i_dir; // 0 -> read, 1 -> write to SPI
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input i_dir; // 0 -> read, 1 -> write to SPI
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input i_recycle; // 0 = 20ns, 1 = 50ns
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input i_recycle; // 0 = 20ns, 1 = 50ns
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output reg [31:0] o_word;
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output reg [31:0] o_word;
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output reg o_valid;
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output reg o_valid;
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output reg o_busy;
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output reg o_busy;
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// Interface with the QSPI lines
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// Interface with the QSPI lines
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output reg o_sck;
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output reg o_sck;
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output reg o_cs_n;
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output reg o_cs_n;
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output reg [1:0] o_mod;
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output reg [1:0] o_mod;
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output reg [3:0] o_dat;
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output reg [3:0] o_dat;
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input [3:0] i_dat;
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input [3:0] i_dat;
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// output wire [22:0] o_dbg;
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// output wire [22:0] o_dbg;
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// assign o_dbg = { state, spi_len,
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// assign o_dbg = { state, spi_len,
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// o_busy, o_valid, o_cs_n, o_sck, o_mod, o_dat, i_dat };
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// o_busy, o_valid, o_cs_n, o_sck, o_mod, o_dat, i_dat };
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wire i_miso;
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wire i_miso;
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assign i_miso = i_dat[1];
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assign i_miso = i_dat[1];
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// These are used in creating a delayed input.
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// These are used in creating a delayed input.
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reg rd_input, rd_spd, rd_valid;
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reg rd_input, rd_spd, rd_valid;
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reg r_spd, r_dir;
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reg r_spd, r_dir;
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reg [3:0] r_recycle;
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reg [3:0] r_recycle;
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reg [5:0] spi_len;
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reg [5:0] spi_len;
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reg [31:0] r_word;
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reg [31:0] r_word;
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reg [30:0] r_input;
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reg [30:0] r_input;
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reg [2:0] state;
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reg [2:0] state;
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initial state = `EQSPI_IDLE;
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initial state = `EQSPI_IDLE;
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initial o_sck = 1'b1;
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initial o_sck = 1'b1;
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initial o_cs_n = 1'b1;
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initial o_cs_n = 1'b1;
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initial o_dat = 4'hd;
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initial o_dat = 4'hd;
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initial rd_valid = 1'b0;
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initial rd_valid = 1'b0;
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initial o_busy = 1'b0;
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initial o_busy = 1'b0;
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initial r_input = 31'h000;
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initial r_input = 31'h000;
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initial rd_valid = 1'b0;
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initial rd_valid = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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rd_input <= 1'b0;
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rd_input <= 1'b0;
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rd_spd <= r_spd;
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rd_spd <= r_spd;
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rd_valid <= 1'b0;
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rd_valid <= 1'b0;
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if ((state == `EQSPI_IDLE)&&(o_sck))
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if ((state == `EQSPI_IDLE)&&(o_sck))
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begin
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begin
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o_cs_n <= 1'b1;
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o_cs_n <= 1'b1;
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o_busy <= 1'b0;
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o_busy <= 1'b0;
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o_mod <= `EQSPI_MOD_SPI;
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o_mod <= `EQSPI_MOD_SPI;
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r_word <= i_word;
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r_word <= i_word;
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r_spd <= i_spd;
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r_spd <= i_spd;
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r_dir <= i_dir;
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r_dir <= i_dir;
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o_dat <= 4'hc;
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o_dat <= 4'hc;
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r_recycle <= (i_recycle)? 4'h8 : 4'h2; // 4'ha : 4'h4
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r_recycle <= (i_recycle)? 4'h8 : 4'h2; // 4'ha : 4'h4
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spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8;
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spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8;
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o_sck <= 1'b1;
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o_sck <= 1'b1;
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if (i_wr)
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if (i_wr)
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begin
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begin
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state <= `EQSPI_START;
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state <= `EQSPI_START;
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o_cs_n <= 1'b0;
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o_cs_n <= 1'b0;
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o_busy <= 1'b1;
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o_busy <= 1'b1;
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end
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end
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end else if (state == `EQSPI_START)
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end else if (state == `EQSPI_START)
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begin // We come in here with sck high, stay here 'til sck is low
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begin // We come in here with sck high, stay here 'til sck is low
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o_sck <= 1'b0;
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o_sck <= 1'b0;
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if (o_sck == 1'b0)
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if (o_sck == 1'b0)
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begin
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begin
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state <= `EQSPI_BITS;
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state <= `EQSPI_BITS;
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spi_len<= spi_len - ( (r_spd)? 6'h4 : 6'h1 );
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spi_len<= spi_len - ( (r_spd)? 6'h4 : 6'h1 );
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if (r_spd)
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if (r_spd)
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r_word <= { r_word[27:0], 4'h0 };
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r_word <= { r_word[27:0], 4'h0 };
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else
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else
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r_word <= { r_word[30:0], 1'b0 };
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r_word <= { r_word[30:0], 1'b0 };
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end
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end
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o_mod <= (r_spd) ? { 1'b1, r_dir } : `EQSPI_MOD_SPI;
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o_mod <= (r_spd) ? { 1'b1, r_dir } : `EQSPI_MOD_SPI;
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o_cs_n <= 1'b0;
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o_cs_n <= 1'b0;
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o_busy <= 1'b1;
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o_busy <= 1'b1;
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if (r_spd)
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if (r_spd)
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o_dat <= r_word[31:28];
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o_dat <= r_word[31:28];
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else
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else
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o_dat <= { 3'b110, r_word[31] };
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o_dat <= { 3'b110, r_word[31] };
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end else if (~o_sck)
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end else if (~o_sck)
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begin
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begin
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o_sck <= 1'b1;
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o_sck <= 1'b1;
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o_busy <= ((state != `EQSPI_READY)||(~i_wr));
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o_busy <= ((state != `EQSPI_READY)||(~i_wr));
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end else if (state == `EQSPI_BITS)
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end else if (state == `EQSPI_BITS)
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begin
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begin
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// Should enter into here with at least a spi_len
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// Should enter into here with at least a spi_len
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// of one, perhaps more
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// of one, perhaps more
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o_sck <= 1'b0;
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o_sck <= 1'b0;
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o_busy <= 1'b1;
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o_busy <= 1'b1;
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if (r_spd)
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if (r_spd)
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begin
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begin
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o_dat <= r_word[31:28];
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o_dat <= r_word[31:28];
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r_word <= { r_word[27:0], 4'h0 };
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r_word <= { r_word[27:0], 4'h0 };
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spi_len <= spi_len - 6'h4;
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spi_len <= spi_len - 6'h4;
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if (spi_len == 6'h4)
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if (spi_len == 6'h4)
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state <= `EQSPI_READY;
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state <= `EQSPI_READY;
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end else begin
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end else begin
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o_dat <= { 3'b110, r_word[31] };
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o_dat <= { 3'b110, r_word[31] };
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r_word <= { r_word[30:0], 1'b0 };
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r_word <= { r_word[30:0], 1'b0 };
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spi_len <= spi_len - 6'h1;
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spi_len <= spi_len - 6'h1;
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if (spi_len == 6'h1)
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if (spi_len == 6'h1)
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state <= `EQSPI_READY;
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state <= `EQSPI_READY;
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end
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end
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rd_input <= 1'b1;
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rd_input <= 1'b1;
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end else if (state == `EQSPI_READY)
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end else if (state == `EQSPI_READY)
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begin
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begin
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o_cs_n <= 1'b0;
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o_cs_n <= 1'b0;
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o_busy <= 1'b1;
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o_busy <= 1'b1;
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// This is the state on the last clock (both low and
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// This is the state on the last clock (both low and
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// high clocks) of the data. Data is valid during
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// high clocks) of the data. Data is valid during
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// this state. Here we chose to either STOP or
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// this state. Here we chose to either STOP or
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// continue and transmit more.
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// continue and transmit more.
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o_sck <= (i_hold); // No clocks while holding
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o_sck <= (i_hold); // No clocks while holding
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if((~o_busy)&&(i_wr))// Acknowledge a new request
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if((~o_busy)&&(i_wr))// Acknowledge a new request
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begin
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begin
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state <= `EQSPI_BITS;
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state <= `EQSPI_BITS;
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o_busy <= 1'b1;
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o_busy <= 1'b1;
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o_sck <= 1'b0;
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o_sck <= 1'b0;
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// Read the new request off the bus
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// Read the new request off the bus
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r_spd <= i_spd;
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r_spd <= i_spd;
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r_dir <= i_dir;
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r_dir <= i_dir;
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// Set up the first bits on the bus
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// Set up the first bits on the bus
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o_mod <= (i_spd) ? { 1'b1, i_dir } : `EQSPI_MOD_SPI;
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o_mod <= (i_spd) ? { 1'b1, i_dir } : `EQSPI_MOD_SPI;
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if (i_spd)
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if (i_spd)
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begin
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begin
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o_dat <= i_word[31:28];
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o_dat <= i_word[31:28];
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r_word <= { i_word[27:0], 4'h0 };
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r_word <= { i_word[27:0], 4'h0 };
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// spi_len <= spi_len - 4;
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// spi_len <= spi_len - 4;
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spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8
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spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8
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- 6'h4;
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- 6'h4;
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end else begin
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end else begin
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o_dat <= { 3'b110, i_word[31] };
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o_dat <= { 3'b110, i_word[31] };
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r_word <= { i_word[30:0], 1'b0 };
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r_word <= { i_word[30:0], 1'b0 };
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spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8
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spi_len<= { 1'b0, i_len, 3'b000 } + 6'h8
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- 6'h1;
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- 6'h1;
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end
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end
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// Read a bit upon any transition
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// Read a bit upon any transition
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rd_input <= 1'b1;
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rd_input <= 1'b1;
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rd_valid <= 1'b1;
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rd_valid <= 1'b1;
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end else begin
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end else begin
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o_sck <= 1'b1;
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o_sck <= 1'b1;
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state <= (i_hold)?`EQSPI_HOLDING : `EQSPI_STOP;
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state <= (i_hold)?`EQSPI_HOLDING : `EQSPI_STOP;
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o_busy <= (~i_hold);
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o_busy <= (~i_hold);
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|
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// Read a bit upon any transition
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// Read a bit upon any transition
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rd_valid <= 1'b1;
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rd_valid <= 1'b1;
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rd_input <= 1'b1;
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rd_input <= 1'b1;
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end
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end
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end else if (state == `EQSPI_HOLDING)
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end else if (state == `EQSPI_HOLDING)
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begin
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begin
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// We need this state so that the o_valid signal
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// We need this state so that the o_valid signal
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// can get strobed with our last result. Otherwise
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// can get strobed with our last result. Otherwise
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// we could just sit in READY waiting for a new command.
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// we could just sit in READY waiting for a new command.
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//
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//
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// Incidentally, the change producing this state was
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// Incidentally, the change producing this state was
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// the result of a nasty race condition. See the
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// the result of a nasty race condition. See the
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// commends in wbqspiflash for more details.
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// commends in wbqspiflash for more details.
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//
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//
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rd_valid <= 1'b0;
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rd_valid <= 1'b0;
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o_cs_n <= 1'b0;
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o_cs_n <= 1'b0;
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o_busy <= 1'b0;
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o_busy <= 1'b0;
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if((~o_busy)&&(i_wr))// Acknowledge a new request
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if((~o_busy)&&(i_wr))// Acknowledge a new request
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begin
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begin
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state <= `EQSPI_BITS;
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state <= `EQSPI_BITS;
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o_busy <= 1'b1;
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o_busy <= 1'b1;
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o_sck <= 1'b0;
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o_sck <= 1'b0;
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|
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// Read the new request off the bus
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// Read the new request off the bus
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r_spd <= i_spd;
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r_spd <= i_spd;
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r_dir <= i_dir;
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r_dir <= i_dir;
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// Set up the first bits on the bus
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// Set up the first bits on the bus
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o_mod<=(i_spd)?{ 1'b1, i_dir } : `EQSPI_MOD_SPI;
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o_mod<=(i_spd)?{ 1'b1, i_dir } : `EQSPI_MOD_SPI;
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if (i_spd)
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if (i_spd)
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begin
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begin
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o_dat <= i_word[31:28];
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o_dat <= i_word[31:28];
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r_word <= { i_word[27:0], 4'h0 };
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r_word <= { i_word[27:0], 4'h0 };
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spi_len<= { 1'b0, i_len, 3'b100 };
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spi_len<= { 1'b0, i_len, 3'b100 };
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end else begin
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end else begin
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o_dat <= { 3'b110, i_word[31] };
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o_dat <= { 3'b110, i_word[31] };
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r_word <= { i_word[30:0], 1'b0 };
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r_word <= { i_word[30:0], 1'b0 };
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spi_len<= { 1'b0, i_len, 3'b111 };
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spi_len<= { 1'b0, i_len, 3'b111 };
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end
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end
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end else begin
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end else begin
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o_sck <= 1'b1;
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o_sck <= 1'b1;
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state <= (i_hold)?`EQSPI_HOLDING : `EQSPI_STOP;
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state <= (i_hold)?`EQSPI_HOLDING : `EQSPI_STOP;
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o_busy <= (~i_hold);
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o_busy <= (~i_hold);
|
end
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end
|
end else if (state == `EQSPI_STOP)
|
end else if (state == `EQSPI_STOP)
|
begin
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begin
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o_sck <= 1'b1; // Stop the clock
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o_sck <= 1'b1; // Stop the clock
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rd_valid <= 1'b0; // Output may have just been valid, but no more
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rd_valid <= 1'b0; // Output may have just been valid, but no more
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o_busy <= 1'b1; // Still busy till port is clear
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o_busy <= 1'b1; // Still busy till port is clear
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state <= `EQSPI_STOP_B;
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state <= `EQSPI_STOP_B;
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// Can't change modes for at least one cycle
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// Can't change modes for at least one cycle
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// o_mod <= `EQSPI_MOD_SPI;
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// o_mod <= `EQSPI_MOD_SPI;
|
end else if (state == `EQSPI_STOP_B)
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end else if (state == `EQSPI_STOP_B)
|
begin
|
begin
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o_cs_n <= 1'b1;
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o_cs_n <= 1'b1;
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o_sck <= 1'b1;
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o_sck <= 1'b1;
|
// Do I need this????
|
// Do I need this????
|
// spi_len <= 3; // Minimum CS high time before next cmd
|
// spi_len <= 3; // Minimum CS high time before next cmd
|
state <= `EQSPI_RECYCLE;
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state <= `EQSPI_RECYCLE;
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o_busy <= 1'b1;
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o_busy <= 1'b1;
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o_mod <= `EQSPI_MOD_SPI;
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o_mod <= `EQSPI_MOD_SPI;
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end else begin // Recycle state
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end else begin // Recycle state
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r_recycle <= r_recycle - 1'b1;
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r_recycle <= r_recycle - 1'b1;
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o_cs_n <= 1'b1;
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o_cs_n <= 1'b1;
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o_sck <= 1'b1;
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o_sck <= 1'b1;
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o_busy <= 1'b1;
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o_busy <= 1'b1;
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o_mod <= `EQSPI_MOD_SPI;
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o_mod <= `EQSPI_MOD_SPI;
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o_dat <= 4'hc;
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o_dat <= 4'hc;
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if (r_recycle[3:1] == 3'h0)
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if (r_recycle[3:1] == 3'h0)
|
state <= `EQSPI_IDLE;
|
state <= `EQSPI_IDLE;
|
end
|
end
|
/*
|
/*
|
end else begin // Invalid states, should never get here
|
end else begin // Invalid states, should never get here
|
state <= `EQSPI_STOP;
|
state <= `EQSPI_STOP;
|
o_valid <= 1'b0;
|
o_valid <= 1'b0;
|
o_busy <= 1'b1;
|
o_busy <= 1'b1;
|
o_cs_n <= 1'b1;
|
o_cs_n <= 1'b1;
|
o_sck <= 1'b1;
|
o_sck <= 1'b1;
|
o_mod <= `EQSPI_MOD_SPI;
|
o_mod <= `EQSPI_MOD_SPI;
|
o_dat <= 4'hd;
|
o_dat <= 4'hd;
|
end
|
end
|
*/
|
*/
|
end
|
end
|
|
|
`define EXTRA_DELAY
|
`define EXTRA_DELAY
|
wire rd_input_N, rd_valid_N, r_spd_N;
|
wire rd_input_N, rd_valid_N, r_spd_N;
|
`ifdef EXTRA_DELAY
|
`ifdef EXTRA_DELAY
|
reg [2:0] rd_input_p, rd_valid_p, r_spd_p;
|
reg [2:0] rd_input_p, rd_valid_p, r_spd_p;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
rd_input_p <= { rd_input_p[1:0], rd_input };
|
rd_input_p <= { rd_input_p[1:0], rd_input };
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
rd_valid_p <= { rd_valid_p[1:0], rd_valid };
|
rd_valid_p <= { rd_valid_p[1:0], rd_valid };
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
r_spd_p <= { r_spd_p[1:0], r_spd };
|
r_spd_p <= { r_spd_p[1:0], r_spd };
|
|
|
assign rd_input_N = rd_input_p[2];
|
assign rd_input_N = rd_input_p[2];
|
assign rd_valid_N = rd_valid_p[2];
|
assign rd_valid_N = rd_valid_p[2];
|
assign r_spd_N = r_spd_p[2];
|
assign r_spd_N = r_spd_p[2];
|
`else
|
`else
|
assign rd_input_N = rd_input;
|
assign rd_input_N = rd_input;
|
assign rd_valid_N = rd_valid;
|
assign rd_valid_N = rd_valid;
|
assign r_spd_N = rd_spd;
|
assign r_spd_N = rd_spd;
|
`endif
|
`endif
|
|
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
// if ((state == `EQSPI_IDLE)||(rd_valid_N))
|
// if ((state == `EQSPI_IDLE)||(rd_valid_N))
|
if (o_valid)
|
if (o_valid)
|
r_input <= 31'h00;
|
r_input <= 31'h00;
|
if ((rd_input_N)&&(r_spd_N))
|
if ((rd_input_N)&&(r_spd_N))
|
r_input <= { r_input[26:0], i_dat };
|
r_input <= { r_input[26:0], i_dat };
|
else if (rd_input_N)
|
else if (rd_input_N)
|
r_input <= { r_input[29:0], i_miso };
|
r_input <= { r_input[29:0], i_miso };
|
|
|
if ((rd_valid_N)&&(r_spd_N))
|
if ((rd_valid_N)&&(r_spd_N))
|
o_word <= { r_input[27:0], i_dat };
|
o_word <= { r_input[27:0], i_dat };
|
else if (rd_valid_N)
|
else if (rd_valid_N)
|
o_word <= { r_input[30:0], i_miso };
|
o_word <= { r_input[30:0], i_miso };
|
o_valid <= rd_valid_N;
|
o_valid <= rd_valid_N;
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
|
|
