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module ram_wb ( dat_i, dat_o, adr_i, we_i, sel_i, cyc_i, stb_i, ack_o, cti_i, clk_i, rst_i);
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parameter dat_width = `RAM_WB_DAT_WIDTH;
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module RAM_wb ( dat_i, dat_o, adr_i, we_i, sel_i, cyc_i, stb_i, ack_o, cti_i, clk_i, rst_i);
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parameter adr_width = `RAM_WB_ADR_WIDTH;
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parameter mem_size = `RAM_WB_MEM_SIZE;
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parameter ram_wb_adr_width = `RAM_WB_ADR_WIDTH;
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parameter ram_wb_mem_size = `RAM_WB_MEM_SIZE;
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parameter ram_wb_dat_width = `RAM_WB_DAT_WIDTH;
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// wishbone signals
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// wishbone signals
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input [31:0] dat_i;
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input [31:0] dat_i;
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output [31:0] dat_o;
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output [31:0] dat_o;
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input [ram_wb_adr_width-1:2] adr_i;
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input [adr_width-1:2] adr_i;
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input we_i;
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input we_i;
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input [3:0] sel_i;
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input [3:0] sel_i;
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input cyc_i;
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input cyc_i;
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input stb_i;
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input stb_i;
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output reg ack_o;
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output reg ack_o;
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assign wr_data[31:24] = sel_i[3] ? dat_i[31:24] : dat_o[31:24];
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assign wr_data[31:24] = sel_i[3] ? dat_i[31:24] : dat_o[31:24];
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assign wr_data[23:16] = sel_i[2] ? dat_i[23:16] : dat_o[23:16];
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assign wr_data[23:16] = sel_i[2] ? dat_i[23:16] : dat_o[23:16];
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assign wr_data[15: 8] = sel_i[1] ? dat_i[15: 8] : dat_o[15: 8];
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assign wr_data[15: 8] = sel_i[1] ? dat_i[15: 8] : dat_o[15: 8];
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assign wr_data[ 7: 0] = sel_i[0] ? dat_i[ 7: 0] : dat_o[ 7: 0];
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assign wr_data[ 7: 0] = sel_i[0] ? dat_i[ 7: 0] : dat_o[ 7: 0];
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//vfifo_dual_port_ram_sc_dw
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ram_wb_sc_dw
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/* #
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(
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.DATA_WIDTH(32),
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.ADDR_WIDTH(11)
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)*/
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ram
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ram
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#
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(
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(
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.d_a(wr_data),
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.DATA_WIDTH(dat_width),
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.q_a(),
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.ADDR_WIDTH(adr_width),
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.adr_a(adr_i),
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.MEM_SIZE(mem_size)
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.we_a(we_i & ack_o),
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)
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.q_b(dat_o),
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ram0
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.adr_b(adr_i),
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(
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.d_b(32'h0),
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.dat_i(wr_data),
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.we_b(1'b0),
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.dat_o(dat_o),
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.adr_i(adr_i),
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.we_i(we_i & ack_o),
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.clk(clk_i)
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.clk(clk_i)
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);
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);
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// ack_o
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// ack_o
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always @ (posedge clk_i or posedge rst_i)
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always @ (posedge clk_i or posedge rst_i)
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if (rst_i)
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if (rst_i)
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ack_o <= 1'b0;
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ack_o <= 1'b0;
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else
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else
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if (!ack_o)
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if (!ack_o) begin
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if (cyc_i & stb_i)
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if (cyc_i & stb_i)
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ack_o <= 1'b1;
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ack_o <= 1'b1; end
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else
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else
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if ((sel_i != 4'b1111) | (ct_i == 3'b000) | (cti_i == 3'b111))
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if ((sel_i != 4'b1111) | (cti_i == 3'b000) | (cti_i == 3'b111))
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ack_o <= 1'b0;
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ack_o <= 1'b0;
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endmodule
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endmodule
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