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https://opencores.org/ocsvn/ram_wb/ram_wb/trunk
[/] [ram_wb/] [trunk/] [rtl/] [verilog/] [ram_wb_sc_dw.v] - Diff between revs 2 and 4
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module RAM_wb_sc_dw
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(
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d_a,
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q_a,
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adr_a,
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we_a,
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q_b,
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adr_b,
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d_b,
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we_b,
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clk
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);
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parameter DATA_WIDTH = 32;
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parameter ADDR_WIDTH = 11;
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parameter MEM_SIZE = 2048;
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input [(DATA_WIDTH-1):0] d_a;
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input [(ADDR_WIDTH-1):0] adr_a;
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input [(ADDR_WIDTH-1):0] adr_b;
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input we_a;
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output [(DATA_WIDTH-1):0] q_b;
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input [(DATA_WIDTH-1):0] d_b;
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output reg [(DATA_WIDTH-1):0] q_a;
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input we_b;
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input clk;
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reg [(DATA_WIDTH-1):0] q_b;
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reg [DATA_WIDTH-1:0] ram [0:MEM_SIZE - 1] ;
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always @ (posedge clk)
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begin
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q_a <= ram[adr_a];
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if (we_a)
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ram[adr_a] <= d_a;
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end
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always @ (posedge clk)
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begin
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q_b <= ram[adr_b];
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if (we_b)
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ram[adr_b] <= d_b;
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end
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endmodule
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