| Line 31... |
Line 31... |
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
// wrapper for the above dual port RAM
|
// wrapper for the above dual port RAM
|
module ram (dat_i, dat_o, adr_i, we_i, rst, clk );
|
module ram (dat_i, dat_o, adr_i, we_i, clk );
|
|
|
parameter dat_width = 32;
|
parameter dat_width = 32;
|
parameter adr_width = 11;
|
parameter adr_width = 11;
|
parameter mem_size = 2048;
|
parameter mem_size = 2048;
|
|
|
input [dat_width-1:0] dat_i;
|
input [dat_width-1:0] dat_i;
|
input [adr_width-1:0] adr_i;
|
input [adr_width-1:0] adr_i;
|
input we_i;
|
input we_i;
|
output [dat_width-1:0] dat_o;
|
output [dat_width-1:0] dat_o;
|
input rst;
|
|
input clk;
|
input clk;
|
|
|
reg sel;
|
|
wire [dat_width-1:0] q_a, q_b;
|
|
|
|
// when adr_i[adr_width-1] = 0 => use a side
|
|
// when adr_i[adr_width-1] = 1 => use b side
|
|
// delay one clock cycle since read has one pipeline stage
|
|
always @ (posedge clk or posedge rst)
|
|
if (rst)
|
|
sel <= 1'b0;
|
|
else
|
|
sel <= adr_i[adr_width-1];
|
|
|
|
assign dat_o = !sel ? q_a : q_b;
|
|
|
|
ram_sc_dw
|
ram_sc_dw
|
#
|
#
|
(
|
(
|
.dat_width(dat_width),
|
.dat_width(dat_width),
|
.adr_width(adr_width-1),
|
.adr_width(adr_width),
|
.mem_size(mem_size/2)
|
.mem_size(mem_size)
|
)
|
)
|
ram0
|
ram0
|
(
|
(
|
.d_a(dat_i),
|
.d_a(dat_i),
|
.q_a(q_a),
|
.q_a(),
|
.adr_a(adr_i[adr_width-2:0]),
|
.adr_a(adr_i),
|
.we_a(we_i & !adr_i[adr_width-1]),
|
.we_a(we_i),
|
.q_b(q_b),
|
.q_b(dat_o),
|
.adr_b(adr_i[adr_width-2:0]),
|
.adr_b(adr_i),
|
.d_b(dat_i),
|
.d_b({dat_width{1'b0}}),
|
.we_b(we_i & adr_i[adr_width-1]),
|
.we_b(1'b0),
|
.clk(clk)
|
.clk(clk)
|
);
|
);
|
|
|
endmodule // ram
|
endmodule // ram
|
|
|
No newline at end of file
|
No newline at end of file
|
