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// True dual port RAM as found in ACTEL proasic3 devices
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// True dual port RAM as found in ACTEL proasic3 devices
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module ram_sc_dw (d_a, q_a, adr_a, we_a, q_b, adr_b, d_b, we_b, clk);
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module ram_sc_dw (d_a, q_a, adr_a, we_a, q_b, adr_b, d_b, we_b, clk);
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parameter dat_width = 32;
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parameter dat_width = `RAM_WB_DAT_WIDTH;
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parameter adr_width = 11;
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parameter adr_width = `RAM_WB_ADR_WIDTH;
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parameter mem_size = 2048;
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parameter mem_size = `RAM_WB_MEM_SIZE;
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input [dat_width-1:0] d_a;
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input [dat_width-1:0] d_a;
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input [adr_width-1:0] adr_a;
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input [adr_width-1:0] adr_a;
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input [adr_width-1:0] adr_b;
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input [adr_width-1:0] adr_b;
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input we_a;
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input we_a;
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input [dat_width-1:0] d_b;
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input [dat_width-1:0] d_b;
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output reg [dat_width-1:0] q_a;
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output reg [dat_width-1:0] q_a;
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input we_b;
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input we_b;
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input clk;
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input clk;
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reg [dat_width-1:0] ram [0:mem_size - 1] ;
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reg [dat_width-1:0] ram [0:mem_size - 1] /*synthesis syn_ramstyle = "no_rw_check"*/;
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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q_a <= ram[adr_a];
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q_a <= ram[adr_a];
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if (we_a)
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if (we_a)
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ram[adr_a] <= d_a;
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ram[adr_a] <= d_a;
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end
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end
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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q_b <= ram[adr_b];
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q_b <= ram[adr_b];
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if (we_b)
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if (we_b)
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ram[adr_b] <= d_b;
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ram[adr_b] <= d_b;
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end
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end
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endmodule
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endmodule
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// wrapper for the above dual port RAM
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module ram (dat_i, dat_o, adr_i, we_i, clk );
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parameter dat_width = 32;
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parameter adr_width = 11;
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parameter mem_size = 2048;
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input [dat_width-1:0] dat_i;
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input [adr_width-1:0] adr_i;
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input we_i;
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output [dat_width-1:0] dat_o;
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input clk;
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ram_sc_dw
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#
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(
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.dat_width(dat_width),
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.adr_width(adr_width),
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.mem_size(mem_size)
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)
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ram0
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(
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.d_a(dat_i),
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.q_a(),
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.adr_a(adr_i),
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.we_a(we_i),
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.q_b(dat_o),
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.adr_b(adr_i),
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.d_b({dat_width{1'b0}}),
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.we_b(1'b0),
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.clk(clk)
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);
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endmodule // ram
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