URL
https://opencores.org/ocsvn/rc4-prbs/rc4-prbs/trunk
[/] [rc4-prbs/] [trunk/] [rc4.v] - Diff between revs 17 and 18
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| Rev 17 |
Rev 18 |
| Line 39... |
Line 39... |
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// Key
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// Key
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reg [7:0] key[0:`KEY_SIZE-1];
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reg [7:0] key[0:`KEY_SIZE-1];
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// S array
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// S array
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reg [7:0] S[0:256];
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reg [7:0] S[0:256];
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reg [9:0] discardCount;
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reg [10:0] discardCount;
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// Key-scheduling state
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// Key-scheduling state
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`define KSS_KEYREAD 4'h0
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`define KSS_KEYREAD 4'h0
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`define KSS_KEYSCHED1 4'h1
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`define KSS_KEYSCHED1 4'h1
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`define KSS_KEYSCHED2 4'h2
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`define KSS_KEYSCHED2 4'h2
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| Line 109... |
Line 109... |
if (i == 8'hFF)
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if (i == 8'hFF)
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begin
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begin
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KSState <= `KSS_CRYPTO;
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KSState <= `KSS_CRYPTO;
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i <= 8'h01;
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i <= 8'h01;
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j <= S[1];
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j <= S[1];
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discardCount <= 10'h0;
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discardCount <= 11'h0;
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output_ready <= 0; // K not valid yet
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output_ready <= 0; // K not valid yet
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end
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end
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else begin
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else begin
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i <= i + 1;
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i <= i + 1;
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KSState <= `KSS_KEYSCHED2;
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KSState <= `KSS_KEYSCHED2;
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| Line 132... |
Line 132... |
*/
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*/
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`KSS_CRYPTO: begin
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`KSS_CRYPTO: begin
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S[i] <= S[j];
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S[i] <= S[j];
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S[j] <= S[i]; // We can do this because of verilog.
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S[j] <= S[i]; // We can do this because of verilog.
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K <= S[ S[i]+S[j] ];
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K <= S[ S[i]+S[j] ];
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if (discardCount<10'h3E8) // discard first 1000 values
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if (discardCount<11'h600) // discard first 1536 values / RFC 4345
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discardCount<=discardCount+1;
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discardCount<=discardCount+1;
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else output_ready <= 1; // Valid K at output
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else output_ready <= 1; // Valid K at output
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i <= i+1;
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i <= i+1;
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// Here is the secret of 1-clock: we develop all possible values of j in the future
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// Here is the secret of 1-clock: we develop all possible values of j in the future
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if (j==i+1)
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if (j==i+1)
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j <= (j + S[i]);
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j <= (j + S[i]);
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else
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else
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if (i==255) j <= (j + S[0]);
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if (i==255) j <= (j + S[0]);
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else j <= (j + S[i+1]);
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else j <= (j + S[i+1]);
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$display ("rc4: output = %08X",K);
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//$display ("rc4: output = %08X",K);
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end
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end
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default: begin
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default: begin
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end
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end
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endcase
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endcase
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end
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end
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