| Line 53... |
Line 53... |
parameter STORE1 = 6'd9;
|
parameter STORE1 = 6'd9;
|
parameter STORE1a = 6'd10;
|
parameter STORE1a = 6'd10;
|
parameter STORE2 = 6'd11;
|
parameter STORE2 = 6'd11;
|
parameter OUTER_INDEXING = 6'd12;
|
parameter OUTER_INDEXING = 6'd12;
|
parameter OUTER_INDEXING2 = 6'd13;
|
parameter OUTER_INDEXING2 = 6'd13;
|
|
parameter DIV1 = 6'd16;
|
|
parameter DIV2 = 6'd17;
|
|
parameter DIV3 = 6'd18;
|
|
parameter MUL2 = 6'd20;
|
parameter ICACHE1 = 6'd31;
|
parameter ICACHE1 = 6'd31;
|
parameter ICACHE2 = 6'd32;
|
parameter ICACHE2 = 6'd32;
|
parameter ICACHE3 = 6'd33;
|
parameter ICACHE3 = 6'd33;
|
parameter ICACHE4 = 6'd34;
|
parameter ICACHE4 = 6'd34;
|
parameter ICACHE5 = 6'd35;
|
parameter ICACHE5 = 6'd35;
|
| Line 106... |
Line 110... |
wire [`HEXBYTE] insn;
|
wire [`HEXBYTE] insn;
|
wire icacheOn = 1'b1;
|
wire icacheOn = 1'b1;
|
reg [`TRPBYTE] ibufadr, icwa;
|
reg [`TRPBYTE] ibufadr, icwa;
|
reg [191:0] ibuf;
|
reg [191:0] ibuf;
|
wire ibufhit = ibufadr==pc;
|
wire ibufhit = ibufadr==pc;
|
reg natMd,firqMd;
|
reg natMd,firqMd,iplMd,dbz,iop;
|
reg md32;
|
reg md32;
|
wire [`DBLBYTE] mask = 24'hFFFFFF;
|
wire [`DBLBYTE] mask = 24'hFFFFFF;
|
reg [1:0] ipg;
|
reg [1:0] ipg;
|
reg isFar;
|
reg isFar;
|
reg isOuterIndexed;
|
reg isOuterIndexed;
|
| Line 121... |
Line 125... |
`ifdef TWELVEBIT
|
`ifdef TWELVEBIT
|
wire [`LOBYTE] ir12 = ir[`LOBYTE];
|
wire [`LOBYTE] ir12 = ir[`LOBYTE];
|
`endif
|
`endif
|
reg [`LOBYTE] dpr; // direct page register
|
reg [`LOBYTE] dpr; // direct page register
|
reg [`DBLBYTE] usppg; // user stack pointer page
|
reg [`DBLBYTE] usppg; // user stack pointer page
|
|
|
|
Address [3:0] brkad; // breakpoint addresses
|
|
brkCtrl [3:0] brkctrl;
|
|
|
wire [`LOBYTE] ndxbyte;
|
wire [`LOBYTE] ndxbyte;
|
reg cf,vf,zf,nf,hf,ef;
|
reg cf,vf,zf,nf,hf,ef;
|
wire [`LOBYTE] cfx8 = cf;
|
wire [`LOBYTE] cfx8 = cf;
|
wire [`DBLBYTE] cfx24 = {23'b0,cf};
|
wire [`DBLBYTE] cfx24 = {23'b0,cf};
|
reg im,firqim;
|
reg im,im1,firqim;
|
|
reg dm; // decimal mode
|
reg sync_state,wait_state;
|
reg sync_state,wait_state;
|
wire [`LOBYTE] ccr = {ef,firqim,hf,im,nf,zf,vf,cf};
|
wire [`LOBYTE] ccr = bitsPerByte==12 ? {2'b00,im1,dm,ef,firqim,hf,im,nf,zf,vf,cf} : {ef,firqim,hf,im,nf,zf,vf,cf};
|
reg [`LOBYTE] acca,accb;
|
reg [`LOBYTE] acca,accb;
|
`ifdef SUPPORT_6309
|
`ifdef SUPPORT_6309
|
reg [`LOBYTE] acce,accf;
|
reg [`LOBYTE] acce,accf;
|
`endif
|
`endif
|
reg [`DBLBYTE] accd;
|
reg [`DBLBYTE] accd;
|
| Line 195... |
Line 204... |
// Data input path multiplexing
|
// Data input path multiplexing
|
reg [bitsPerByte-1:0] dati;
|
reg [bitsPerByte-1:0] dati;
|
always_comb
|
always_comb
|
dati = dat_i;
|
dati = dat_i;
|
|
|
|
genvar g;
|
|
|
// Evaluate the branch conditional
|
// Evaluate the branch conditional
|
reg takb;
|
reg takb;
|
always_comb
|
always_comb
|
case(ir12)
|
case(ir12)
|
`BRA,`LBRA: takb <= 1'b1;
|
`BRA,`LBRA: takb <= 1'b1;
|
| Line 369... |
Line 380... |
13'b01???00100010: NdxAddr <= ndxreg - 2'd3;
|
13'b01???00100010: NdxAddr <= ndxreg - 2'd3;
|
13'b01???00000011: NdxAddr <= ndxreg - 2'd2;
|
13'b01???00000011: NdxAddr <= ndxreg - 2'd2;
|
13'b01???00000100: NdxAddr <= ndxreg;
|
13'b01???00000100: NdxAddr <= ndxreg;
|
13'b01???00000101: NdxAddr <= ndxreg + {{BPB*2{accb[BPBM1]}},accb};
|
13'b01???00000101: NdxAddr <= ndxreg + {{BPB*2{accb[BPBM1]}},accb};
|
13'b01???00000110: NdxAddr <= ndxreg + {{BPB*2{acca[BPBM1]}},acca};
|
13'b01???00000110: NdxAddr <= ndxreg + {{BPB*2{acca[BPBM1]}},acca};
|
|
`ifdef SUPPORT_6309
|
|
13'b01???00010101: NdxAddr <= ndxreg + {{BPB*2{accf[BPBM1]}},accf};
|
|
13'b01???00010110: NdxAddr <= ndxreg + {{BPB*2{acce[BPBM1]}},acce};
|
|
13'b01???00011011: NdxAddr <= ndxreg + {acce,accf};
|
|
`endif
|
13'b01???00001000: NdxAddr <= ndxreg + offset12;
|
13'b01???00001000: NdxAddr <= ndxreg + offset12;
|
13'b01???00001001: NdxAddr <= ndxreg + offset24;
|
13'b01???00001001: NdxAddr <= ndxreg + offset24;
|
13'b01???00001010: NdxAddr <= ndxreg + offset36;
|
13'b01???00001010: NdxAddr <= ndxreg + offset36;
|
13'b01???00001011: NdxAddr <= ndxreg + {acca,accb};
|
13'b01???00001011: NdxAddr <= ndxreg + {acca,accb};
|
13'b01???00001100: NdxAddr <= pc + offset12 + 3'd3;
|
13'b01???00001100: NdxAddr <= pc + offset12 + 3'd3;
|
| Line 385... |
Line 401... |
13'b01???10000010: NdxAddr <= 24'd0;
|
13'b01???10000010: NdxAddr <= 24'd0;
|
13'b01???10000011: NdxAddr <= 24'd0;
|
13'b01???10000011: NdxAddr <= 24'd0;
|
13'b01???10000100: NdxAddr <= 24'd0;
|
13'b01???10000100: NdxAddr <= 24'd0;
|
13'b01???10000101: NdxAddr <= {{BPB*2{accb[BPBM1]}},accb};
|
13'b01???10000101: NdxAddr <= {{BPB*2{accb[BPBM1]}},accb};
|
13'b01???10000110: NdxAddr <= {{BPB*2{acca[BPBM1]}},acca};
|
13'b01???10000110: NdxAddr <= {{BPB*2{acca[BPBM1]}},acca};
|
|
`ifdef SUPPORT_6309
|
|
13'b01???10010101: NdxAddr <= {{BPB*2{accf[BPBM1]}},accf};
|
|
13'b01???10010110: NdxAddr <= {{BPB*2{acce[BPBM1]}},acce};
|
|
13'b01???10011011: NdxAddr <= {acce,accf};
|
|
`endif
|
13'b01???10001000: NdxAddr <= offset12;
|
13'b01???10001000: NdxAddr <= offset12;
|
13'b01???10001001: NdxAddr <= offset24;
|
13'b01???10001001: NdxAddr <= offset24;
|
13'b01???10001010: NdxAddr <= offset36;
|
13'b01???10001010: NdxAddr <= offset36;
|
13'b01???10001011: NdxAddr <= {acca,accb};
|
13'b01???10001011: NdxAddr <= {acca,accb};
|
13'b01???10001100: NdxAddr <= pc + offset12 + 3'd3;
|
13'b01???10001100: NdxAddr <= pc + offset12 + 3'd3;
|
| Line 446... |
Line 467... |
12'b1???00000000: insnsz <= 4'h2;
|
12'b1???00000000: insnsz <= 4'h2;
|
12'b1???00000001: insnsz <= 4'h2;
|
12'b1???00000001: insnsz <= 4'h2;
|
12'b1???00000010: insnsz <= 4'h2;
|
12'b1???00000010: insnsz <= 4'h2;
|
12'b1???00000011: insnsz <= 4'h2;
|
12'b1???00000011: insnsz <= 4'h2;
|
12'b1???00000100: insnsz <= 4'h2;
|
12'b1???00000100: insnsz <= 4'h2;
|
12'b1???00000101: insnsz <= 4'h2;
|
12'b1???000?0101: insnsz <= 4'h2;
|
12'b1???00000110: insnsz <= 4'h2;
|
12'b1???000?0110: insnsz <= 4'h2;
|
12'b1???00001000: insnsz <= 4'h3;
|
12'b1???00001000: insnsz <= 4'h3;
|
12'b1???00001001: insnsz <= 4'h4;
|
12'b1???00001001: insnsz <= 4'h4;
|
12'b1???00001010: insnsz <= 4'h5;
|
12'b1???00001010: insnsz <= 4'h5;
|
12'b1???00001011: insnsz <= 4'h2;
|
12'b1???000?1011: insnsz <= 4'h2;
|
12'b1???00001100: insnsz <= 4'h3;
|
12'b1???00001100: insnsz <= 4'h3;
|
12'b1???00001101: insnsz <= 4'h4;
|
12'b1???00001101: insnsz <= 4'h4;
|
12'b1???00001110: insnsz <= 4'h5;
|
12'b1???00001110: insnsz <= 4'h5;
|
12'b1??000001111: insnsz <= isFar ? 4'h5 : 4'h4;
|
12'b1??000001111: insnsz <= isFar ? 4'h5 : 4'h4;
|
12'b1??100001111: insnsz <= 4'h4;
|
12'b1??100001111: insnsz <= 4'h4;
|
| Line 470... |
Line 491... |
4'b0001: src1 <= xr;
|
4'b0001: src1 <= xr;
|
4'b0010: src1 <= yr;
|
4'b0010: src1 <= yr;
|
4'b0011: src1 <= usp;
|
4'b0011: src1 <= usp;
|
4'b0100: src1 <= ssp;
|
4'b0100: src1 <= ssp;
|
4'b0101: src1 <= pcp2;
|
4'b0101: src1 <= pcp2;
|
4'b1000: src1 <= acca[`LOBYTE];
|
4'b1000: src1 <= {12'hFFF,acca[`LOBYTE]};
|
4'b1001: src1 <= accb[`LOBYTE];
|
4'b1001: src1 <= {12'hFFF,accb[`LOBYTE]};
|
4'b1010: src1 <= ccr;
|
4'b1010: src1 <= {ccr,ccr};
|
4'b1011: src1 <= dpr;
|
4'b1011: src1 <= {dpr,dpr};
|
4'b1100: src1 <= usppg;
|
4'b1100: src1 <= usppg;
|
4'b1101: src1 <= 24'h0000;
|
4'b1101: src1 <= 24'h0000;
|
`ifdef SUPPORT_6309
|
`ifdef SUPPORT_6309
|
4'b0110: src1 <= {acce[`LOBYTE],accf[`LOBYTE]};
|
4'b0110: src1 <= {acce[`LOBYTE],accf[`LOBYTE]};
|
4'b1110: src1 <= acce;
|
4'b1110: src1 <= {12'hFFF,acce};
|
4'b1111: src1 <= accf;
|
4'b1111: src1 <= {12'hFFF,accf};
|
`else
|
`else
|
4'b1110: src1 <= 24'h0000;
|
4'b1110: src1 <= 24'h0000;
|
4'b1111: src1 <= 24'h0000;
|
4'b1111: src1 <= 24'h0000;
|
`endif
|
`endif
|
default: src1 <= 24'h0000;
|
default: src1 <= 24'h0000;
|
| Line 530... |
Line 551... |
ir12==`SUBA_NDX || ir12==`CMPA_NDX || ir12==`SBCA_NDX || ir12==`ANDA_NDX || ir12==`BITA_NDX ||
|
ir12==`SUBA_NDX || ir12==`CMPA_NDX || ir12==`SBCA_NDX || ir12==`ANDA_NDX || ir12==`BITA_NDX ||
|
ir12==`LDA_NDX || ir12==`EORA_NDX || ir12==`ADCA_NDX || ir12==`ORA_NDX || ir12==`ADDA_NDX ||
|
ir12==`LDA_NDX || ir12==`EORA_NDX || ir12==`ADCA_NDX || ir12==`ORA_NDX || ir12==`ADDA_NDX ||
|
ir12==`SUBA_EXT || ir12==`CMPA_EXT || ir12==`SBCA_EXT || ir12==`ANDA_EXT || ir12==`BITA_EXT ||
|
ir12==`SUBA_EXT || ir12==`CMPA_EXT || ir12==`SBCA_EXT || ir12==`ANDA_EXT || ir12==`BITA_EXT ||
|
ir12==`LDA_EXT || ir12==`EORA_EXT || ir12==`ADCA_EXT || ir12==`ORA_EXT || ir12==`ADDA_EXT
|
ir12==`LDA_EXT || ir12==`EORA_EXT || ir12==`ADCA_EXT || ir12==`ORA_EXT || ir12==`ADDA_EXT
|
;
|
;
|
|
wire isAdc = ir12==`ADCA_IMM || ir12==`ADCA_DP || ir12==`ADCA_NDX || ir12==`ADCA_EXT ||
|
|
ir12==`ADCB_IMM || ir12==`ADCB_DP || ir12==`ADCB_NDX || ir12==`ADCB_EXT ||
|
|
ir12==`ADCD_IMM || ir12==`ADCD_DP || ir12==`ADCD_NDX || ir12==`ADCD_EXT ;
|
|
wire isSbc = ir12==`SBCA_IMM || ir12==`SBCA_DP || ir12==`SBCA_NDX || ir12==`SBCA_EXT ||
|
|
ir12==`SBCB_IMM || ir12==`SBCB_DP || ir12==`SBCB_NDX || ir12==`SBCB_EXT ||
|
|
ir12==`SBCD_IMM || ir12==`SBCD_DP || ir12==`SBCD_NDX || ir12==`SBCD_EXT ;
|
|
|
`ifdef SUPPORT_6309
|
`ifdef SUPPORT_6309
|
wire isAcce = ir12 == `ADDE_IMM || ir12==`ADDE_DP || ir12==`ADDE_NDX || ir12==`ADDE_EXT || ir12==`CLRE || ir12==`COME ||
|
wire isAcce = ir12 == `ADDE_IMM || ir12==`ADDE_DP || ir12==`ADDE_NDX || ir12==`ADDE_EXT || ir12==`CLRE || ir12==`COME ||
|
ir12 == `SUBE_IMM || ir12==`SUBE_DP || ir12==`SUBE_NDX || ir12==`SUBE_EXT ||
|
ir12 == `SUBE_IMM || ir12==`SUBE_DP || ir12==`SUBE_NDX || ir12==`SUBE_EXT ||
|
ir12 == `LDE_IMM || ir12==`LDE_DP || ir12==`LDE_NDX || ir12==`LDE_EXT ||
|
ir12 == `LDE_IMM || ir12==`LDE_DP || ir12==`LDE_NDX || ir12==`LDE_EXT ||
|
| Line 574... |
Line 601... |
wire ihit = hit0 & hit1;
|
wire ihit = hit0 & hit1;
|
reg rhit0;
|
reg rhit0;
|
|
|
assign lic_o = (state==CALC && !isRMW) ||
|
assign lic_o = (state==CALC && !isRMW) ||
|
(state==DECODE && (
|
(state==DECODE && (
|
ir12==`NOP || ir12==`ORCC || ir12==`ANDCC || ir12==`DAA || ir12==`LDMD || ir12==`TFR || ir12==`EXG ||
|
ir12==`NOP || ir12==`ORCC || ir12==`ANDCC || ir12==`DAA || ir12==`LDMD || ir12==`BITMD || ir12==`TFR || ir12==`EXG ||
|
ir12==`NEGA || ir12==`COMA || ir12==`LSRA || ir12==`RORA || ir12==`ASRA || ir12==`ROLA || ir12==`DECA || ir12==`INCA || ir12==`TSTA || ir12==`CLRA ||
|
ir12==`NEGA || ir12==`COMA || ir12==`LSRA || ir12==`RORA || ir12==`ASRA || ir12==`ROLA || ir12==`DECA || ir12==`INCA || ir12==`TSTA || ir12==`CLRA ||
|
ir12==`DECE || ir12==`DECF || ir12==`DECD || ir12==`DECW || ir12==`INCE || ir12==`INCF || ir12==`INCD || ir12==`INCW ||
|
ir12==`DECE || ir12==`DECF || ir12==`DECD || ir12==`DECW || ir12==`INCE || ir12==`INCF || ir12==`INCD || ir12==`INCW ||
|
ir12==`NEGB || ir12==`COMB || ir12==`LSRB || ir12==`RORB || ir12==`ASRB || ir12==`ROLB || ir12==`DECB || ir12==`INCB || ir12==`TSTB || ir12==`CLRB ||
|
ir12==`NEGB || ir12==`COMB || ir12==`LSRB || ir12==`RORB || ir12==`ASRB || ir12==`ROLB || ir12==`DECB || ir12==`INCB || ir12==`TSTB || ir12==`CLRB ||
|
ir12==`COME || ir12==`COMF || ir12==`COMD || ir12==`COMW ||
|
ir12==`COME || ir12==`COMF || ir12==`COMD || ir12==`COMW ||
|
ir12==`ASLD || ir12==`ASRD || ir12==`TSTD || ir12==`ADDR || ir12==`ADCR || ir12==`ANDR ||
|
ir12==`ASLD || ir12==`ASRD || ir12==`TSTD || ir12==`ADDR || ir12==`ADCR || ir12==`ANDR ||
|
| Line 676... |
Line 703... |
.pc(pc),
|
.pc(pc),
|
.hit0(hit0),
|
.hit0(hit0),
|
.hit1(hit1)
|
.hit1(hit1)
|
);
|
);
|
|
|
/* Need to account for signed division
|
wire bcdaddbcf, bcdsuubbcf,bcdaddcf,bcdsubcf,bcdnegcf,bcdnegbcf;
|
reg [35:0] divtbl [0:4095];
|
wire [bitsPerByte-1:0] bcdaddbo, bcdsubbo, bcdnegbo;
|
genvar g;
|
wire [bitsPerByte*2-1:0] bcdaddo, bcdsubo, bcdnego;
|
|
wire [31:0] bcdmulo;
|
|
|
|
`ifdef SUPPORT_BCD
|
|
BCDAddN #(.N(3)) ubcda1 (
|
|
.ci(isAdc ? cf : 1'b0),
|
|
.a(acc),
|
|
.b(b12),
|
|
.o(bcdaddbo),
|
|
.co(bcdaddbcf)
|
|
);
|
|
|
|
BCDAddN #(.N(6)) ubcda2 (
|
|
.ci(isAdc ? cf : 1'b0),
|
|
.a({acca,accb}),
|
|
.b(b),
|
|
.o(bcdaddo),
|
|
.co(bcdaddcf)
|
|
);
|
|
|
|
BCDSubN #(.N(3)) ubcds1 (
|
|
.ci(isSbc ? cf : 1'b0),
|
|
.a(acc),
|
|
.b(b12),
|
|
.o(bcdsubbo),
|
|
.co(bcdsubbcf)
|
|
);
|
|
|
|
BCDSubN #(.N(6)) ubcds2 (
|
|
.ci(isSbc ? cf : 1'b0),
|
|
.a({acca,accb}),
|
|
.b(b),
|
|
.o(bcdsubo),
|
|
.co(bcdsubcf)
|
|
);
|
|
|
|
BCDSubN #(.N(3)) ubcds3 (
|
|
.ci(1'b0),
|
|
.a(12'h0),
|
|
.b(acc),
|
|
.o(bcdnegbo),
|
|
.co(bcdnegbcf)
|
|
);
|
|
|
|
BCDSubN #(.N(6)) ubcds4 (
|
|
.ci(1'b0),
|
|
.a(12'h0),
|
|
.b({acca,accb}),
|
|
.o(bcdnego),
|
|
.co(bcdnegcf)
|
|
);
|
|
|
|
BCDMul4 ubcdmul1
|
|
(
|
|
.a({4'h0,acca}),
|
|
.b({4'h0,accb}),
|
|
.o(bcdmulo)
|
|
);
|
|
`endif
|
|
|
|
reg [bitsPerByte*2-1:0] bcdmul_res [0:15];
|
|
reg [bitsPerByte*2-1:0] bcdmul_res16;
|
|
genvar g5;
|
|
generate begin : gBCDMulPipe
|
|
always_ff @(posedge clk_i)
|
|
bcdmul_res[0] <= bcdmulo[23:0];
|
|
always_ff @(posedge clk_i)
|
|
bcdmul_res16 <= muld_res[15];
|
|
for (g5 = 1; g5 < 16; g5 = g5 + 1)
|
|
always_ff @(posedge clk_i)
|
|
bcdmul_res[g5] = bcdmul_res[g5-1];
|
|
end
|
|
endgenerate
|
|
|
|
// Multiplier logic
|
|
wire signed [`QUADBYTE] muld_prod = $signed({acca,accb}) * $signed(b[`DBLBYTE]);
|
|
reg [`QUADBYTE] muld_res [0:15];
|
|
reg [`QUADBYTE] muld_res6;
|
|
genvar g4;
|
|
generate begin : gMulPipe
|
|
always_ff @(posedge clk_i)
|
|
muld_res[0] <= muld_prod;
|
|
always_ff @(posedge clk_i)
|
|
muld_res6 <= muld_res[5];
|
|
for (g4 = 1; g4 < 6; g4 = g4 + 1)
|
|
always_ff @(posedge clk_i)
|
|
muld_res[g4] = muld_res[g4-1];
|
|
end
|
|
endgenerate
|
|
|
|
// Divider logic
|
|
reg [5:0] divcnt;
|
|
/*
|
|
reg divsign;
|
|
reg [`DBLBYTE] dividend;
|
|
// Table of positive constants 1/0 to 1/2047, accurate to 35 bits
|
|
reg [26:0] divtbl [0:2047];
|
|
genvar g2;
|
generate begin: gDivtbl
|
generate begin: gDivtbl
|
for (g = 0; g < 4096; g = g + 1)
|
for (g2 = 0; g2 < 2048; g2 = g2 + 1)
|
divtbl[g] = 36'h800000000 / g;
|
initial begin
|
|
divtbl[g2] = 27'h4000000 / g2;
|
|
end
|
|
end
|
|
endgenerate
|
|
reg [49:0] divres;
|
|
always_comb
|
|
divres = ({36'd0,dividend} * divtbl[b12]);
|
|
reg [11:0] divrem;
|
|
always_comb
|
|
divrem = dividend - divres[49:26] * b12;
|
|
// Now create an 12-stage divider pipeline. Hopefully the synthesizer
|
|
// will backfill along this pipeline. Each multiplier requires only
|
|
// about 5 stages for best performance.
|
|
genvar g1;
|
|
reg [49:0] divrespipe [0:31];
|
|
reg [11:0] divrempipe [0:31];
|
|
reg [49:0] divres12;
|
|
reg [11:0] divrem12;
|
|
generate begin : gDivPipe
|
|
always_ff @(posedge clk_i)
|
|
divrespipe[0] <= divres;
|
|
always_ff @(posedge clk_i)
|
|
divrempipe[0] <= divrem;
|
|
always_ff @(posedge clk_i)
|
|
divres12 <= divrespipe[12];
|
|
always_ff @(posedge clk_i)
|
|
divrem12 <= divrempipe[12];
|
|
for (g1 = 1; g1 < 13; g1 = g1 + 1)
|
|
always_ff @(posedge clk_i) begin
|
|
divrespipe[g1] <= divrespipe[g1-1];
|
|
divrempipe[g1] <= divrempipe[g1-1];
|
|
end
|
|
end
|
endgenerate
|
endgenerate
|
wire [`DBLBYTE] divres = ({acca,accb} * divtbl[b12]) >> 36;
|
|
wire [11:0] divrem = {acca,accb} - divres * b12;
|
|
*/
|
*/
|
|
wire [23:0] divres24;
|
|
wire [15:0] divrem12;
|
|
wire [47:0] divres48;
|
|
wire [23:0] divrem24;
|
|
wire [15:0] divres16;
|
|
wire [7:0] divrem8;
|
|
wire [31:0] divres32;
|
|
wire [15:0] divrem16;
|
|
|
|
`ifdef SUPPORT_6309
|
|
`ifdef SUPPORT_DIVIDE
|
|
generate begin : gDividers
|
|
if (bitsPerByte==12) begin
|
|
div24by12 udiv24by12 (
|
|
.aclk(clk_i), // input wire aclk
|
|
.s_axis_divisor_tvalid(1'b1), // input wire s_axis_divisor_tvalid
|
|
.s_axis_divisor_tdata({4'h0,b12}), // input wire [15 : 0] s_axis_divisor_tdata
|
|
.s_axis_dividend_tvalid(1'b1), // input wire s_axis_dividend_tvalid
|
|
.s_axis_dividend_tdata({acca,accb}), // input wire [23 : 0] s_axis_dividend_tdata
|
|
.m_axis_dout_tvalid(), // output wire m_axis_dout_tvalid
|
|
.m_axis_dout_tuser(), // output wire [0 : 0] m_axis_dout_tuser
|
|
.m_axis_dout_tdata({divres24,divrem12}) // output wire [39 : 0] m_axis_dout_tdata
|
|
);
|
|
|
|
div48by24 udiv48by24 (
|
|
.aclk(clk_i), // input wire aclk
|
|
.s_axis_divisor_tvalid(1'b1), // input wire s_axis_divisor_tvalid
|
|
.s_axis_divisor_tdata(b), // input wire [23 : 0] s_axis_divisor_tdata
|
|
.s_axis_dividend_tvalid(1'b1), // input wire s_axis_dividend_tvalid
|
|
.s_axis_dividend_tdata({acca,accb,acce,accf}), // input wire [47 : 0] s_axis_dividend_tdata
|
|
.m_axis_dout_tvalid(), // output wire m_axis_dout_tvalid
|
|
.m_axis_dout_tuser(), // output wire [0 : 0] m_axis_dout_tuser
|
|
.m_axis_dout_tdata({divres48,divrem24}) // output wire [71 : 0] m_axis_dout_tdata
|
|
);
|
|
end
|
|
end
|
|
endgenerate
|
|
`endif
|
|
`endif
|
|
|
// For asynchronous reads,
|
// For asynchronous reads,
|
// The read response might come back in any order (the packets could loop
|
// The read response might come back in any order (the packets could loop
|
// around in the network.
|
// around in the network.
|
// We need to buffer and reorder the response correctly.
|
// We need to buffer and reorder the response correctly.
|
| Line 715... |
Line 909... |
icbuf[adr_o[3:0]] <= dati;
|
icbuf[adr_o[3:0]] <= dati;
|
end
|
end
|
`endif
|
`endif
|
end
|
end
|
|
|
genvar g;
|
genvar g3;
|
generate begin : gIcin
|
generate begin : gIcin
|
for (g = 0; g < 16; g = g + 1)
|
for (g3 = 0; g3 < 16; g3 = g3 + 1)
|
always_comb
|
always_comb
|
icbuf2[(g+1)*bitsPerByte-1:g*bitsPerByte] <= icbuf[g];
|
icbuf2[(g3+1)*bitsPerByte-1:g3*bitsPerByte] <= icbuf[g3];
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
// Bus timeout counter
|
// Bus timeout counter
|
always_ff @(posedge clk_i)
|
always_ff @(posedge clk_i)
|
| Line 774... |
Line 968... |
|
|
always_ff @(posedge clk_i)
|
always_ff @(posedge clk_i)
|
tsc_latched <= tsc_i;
|
tsc_latched <= tsc_i;
|
|
|
always_ff @(posedge clk_i)
|
always_ff @(posedge clk_i)
|
nmi1 <= nmi_i;
|
nmi1 <= iplMd ? &{nmi_i,firq_i,irq_i} : nmi_i;
|
always_ff @(posedge clk_i)
|
always_ff @(posedge clk_i)
|
`ifdef SUPPORT_CHECKPOINT
|
`ifdef SUPPORT_CHECKPOINT
|
if (ms_count[9:0]==10'h3FF && chkpoint!=12'h000)
|
if (ms_count[9:0]==10'h3FF && chkpoint!=12'h000)
|
nmi_edge <= 1'b1;
|
nmi_edge <= 1'b1;
|
else
|
else
|
`endif
|
`endif
|
if (nmi_i & !nmi1)
|
if ((iplMd ? &{nmi_i,firq_i,irq_i} : nmi_i) & !nmi1)
|
nmi_edge <= 1'b1;
|
nmi_edge <= 1'b1;
|
else if (state==DECODE && ir12==`INT)
|
else if (state==DECODE && ir12==`INT)
|
nmi_edge <= 1'b0;
|
nmi_edge <= 1'b0;
|
|
|
reg [11:0] rst_cnt;
|
reg [11:0] rst_cnt;
|
|
|
always @(posedge clk_i)
|
always @(posedge clk_i)
|
if (rst_i) begin
|
if (rst_i) begin
|
wb_nack();
|
wb_nack();
|
|
natMd <= 1'b0;
|
|
firqMd <= 1'b0;
|
|
iplMd <= 1'b0;
|
rty <= `FALSE;
|
rty <= `FALSE;
|
rst_cnt <= {id,4'd0};
|
rst_cnt <= {id,4'd0};
|
next_state(RESET);
|
next_state(RESET);
|
sync_state <= `FALSE;
|
sync_state <= `FALSE;
|
wait_state <= `FALSE;
|
wait_state <= `FALSE;
|
| Line 808... |
Line 1005... |
ibufadr <= {BPB*3{1'b0}};
|
ibufadr <= {BPB*3{1'b0}};
|
// pc <= 24'hFFFFFE;
|
// pc <= 24'hFFFFFE;
|
pc <= {{BPB*3-1{1'b1}},1'b0}; // FF...FE
|
pc <= {{BPB*3-1{1'b1}},1'b0}; // FF...FE
|
ir <= {4{`NOP}};
|
ir <= {4{`NOP}};
|
ibuf <= {4{`NOP}};
|
ibuf <= {4{`NOP}};
|
|
dm <= 1'b0;
|
im <= 1'b1;
|
im <= 1'b1;
|
firqim <= 1'b1;
|
firqim <= 1'b1;
|
nmi_armed <= `FALSE;
|
nmi_armed <= `FALSE;
|
ic_invalidate <= `TRUE;
|
ic_invalidate <= `TRUE;
|
first_ifetch <= `TRUE;
|
first_ifetch <= `TRUE;
|
acca <= 12'h0;
|
acca <= 12'h0;
|
accb <= 12'h0;
|
accb <= 12'h0;
|
accd <= 24'h0;
|
accd <= 24'h0;
|
|
`ifdef SUPPORT_6309
|
|
accw <= 24'h0;
|
|
`endif
|
xr <= 24'h0;
|
xr <= 24'h0;
|
yr <= 24'h0;
|
yr <= 24'h0;
|
usppg <= 16'h0;
|
usppg <= 16'h0;
|
usp <= 24'h0;
|
usp <= 24'h0;
|
ssp <= 24'h0;
|
ssp <= 24'h0;
|
| Line 831... |
Line 1032... |
ba_o <= 1'b0;
|
ba_o <= 1'b0;
|
bs_o <= 1'b0;
|
bs_o <= 1'b0;
|
end
|
end
|
outstanding <= 16'h0;
|
outstanding <= 16'h0;
|
iccnt <= 4'h0;
|
iccnt <= 4'h0;
|
|
//dividend <= 'b0;
|
|
divcnt <= 'b0;
|
|
//divsign <= 'b0;
|
end
|
end
|
else begin
|
else begin
|
|
|
// Release any bus lock during the last state of an instruction.
|
// Release any bus lock during the last state of an instruction.
|
if (lic_o && ack_i && (state==STORE2 || state==LOAD2))
|
if (lic_o && ack_i && (state==STORE2 || state==LOAD2))
|
| Line 867... |
Line 1071... |
STORE1a: tStore1a();
|
STORE1a: tStore1a();
|
STORE2: tStore2();
|
STORE2: tStore2();
|
|
|
// ============================================================================
|
// ============================================================================
|
// ============================================================================
|
// ============================================================================
|
|
MUL2:
|
|
if (divcnt != 6'd0)
|
|
divcnt <= divcnt - 2'd1;
|
|
else
|
|
next_state(IFETCH);
|
|
DIV1:
|
|
begin
|
|
/*
|
|
divsign <= acca[bitsPerByte-1] ^ b12[bitsPerByte-1];
|
|
if (acca[bitsPerByte-1])
|
|
dividend <= -{acca,accb};
|
|
else
|
|
dividend <= {acca,accb};
|
|
if (b12[bitsPerByte-1])
|
|
b <= -b;
|
|
*/
|
|
case(ir12)
|
|
`DIVD_IMM,`DIVD_DP,`DIVD_NDX,`DIVD_EXT:
|
|
divcnt <= 6'd28;
|
|
`DIVQ_IMM,`DIVQ_DP,`DIVQ_NDX,`DIVQ_EXT:
|
|
divcnt <= 6'd52;
|
|
endcase
|
|
next_state(DIV2);
|
|
end
|
|
DIV2:
|
|
if (divcnt != 6'd0)
|
|
divcnt <= divcnt - 2'd1;
|
|
else
|
|
next_state(DIV3);
|
|
DIV3:
|
|
begin
|
|
res[`LOBYTE] <= divres24[11:0];
|
|
res[`HIBYTE] <= divrem12;
|
|
vf <= divres24[23:12] != {12{divres24[11]}};
|
|
next_state(IFETCH);
|
|
end
|
|
|
|
// ============================================================================
|
|
// ============================================================================
|
PUSH1:
|
PUSH1:
|
begin
|
begin
|
next_state(PUSH2);
|
next_state(PUSH2);
|
if (isINT | isPSHS) begin
|
if (isINT | isPSHS) begin
|
wadr <= (ssp - cnt);
|
wadr <= (ssp - cnt);
|
| Line 929... |
Line 1172... |
store_what <= isFar ? `SW_PC2316 : `SW_PCH;
|
store_what <= isFar ? `SW_PC2316 : `SW_PCH;
|
ir[bitsPerByte+7] <= 1'b0;
|
ir[bitsPerByte+7] <= 1'b0;
|
end
|
end
|
else begin
|
else begin
|
if (isINT) begin
|
if (isINT) begin
|
|
dm <= 1'b0;
|
radr <= vect;
|
radr <= vect;
|
if (vec_i != 24'h0) begin
|
if (vec_i != 24'h0) begin
|
$display("vector: %h", vec_i);
|
$display("vector: %h", vec_i);
|
pc <= vec_i;
|
pc <= vec_i;
|
next_state(IFETCH);
|
next_state(IFETCH);
|
| Line 1061... |
Line 1305... |
endcase
|
endcase
|
end
|
end
|
12'b1????0000010: radr <= radr + ndxreg;
|
12'b1????0000010: radr <= radr + ndxreg;
|
12'b1????0000011: radr <= radr + ndxreg;
|
12'b1????0000011: radr <= radr + ndxreg;
|
12'b1????0000100: radr <= radr + ndxreg;
|
12'b1????0000100: radr <= radr + ndxreg;
|
12'b1????0000101: radr <= radr + ndxreg;
|
12'b1????00?0101: radr <= radr + ndxreg;
|
12'b1????0000110: radr <= radr + ndxreg;
|
12'b1????00?0110: radr <= radr + ndxreg;
|
12'b1????0001000: radr <= radr + ndxreg;
|
12'b1????0001000: radr <= radr + ndxreg;
|
12'b1????0001001: radr <= radr + ndxreg;
|
12'b1????0001001: radr <= radr + ndxreg;
|
12'b1????0001010: radr <= radr + ndxreg;
|
12'b1????0001010: radr <= radr + ndxreg;
|
12'b1????0001011: radr <= radr + ndxreg;
|
12'b1????00?1011: radr <= radr + ndxreg;
|
default: radr <= radr;
|
default: radr <= radr;
|
endcase
|
endcase
|
end
|
end
|
next_state(OUTER_INDEXING2);
|
next_state(OUTER_INDEXING2);
|
end
|
end
|
| Line 1324... |
Line 1568... |
bs_o <= 1'b1;
|
bs_o <= 1'b1;
|
ir[`LOBYTE] <= `INT;
|
ir[`LOBYTE] <= `INT;
|
ipg <= 2'b11;
|
ipg <= 2'b11;
|
vect <= `NMI_VECT;
|
vect <= `NMI_VECT;
|
end
|
end
|
|
else if ({nmi_i,firq_i,irq_i} > {im1,firqim,im} && !sync_state && iplMd) begin
|
|
bs_o <= 1'b1;
|
|
ir[`LOBYTE] <= `INT;
|
|
ipg <= 2'b11;
|
|
case({nmi_i,firq_i,irq_i})
|
|
3'd1: vect <= `IRQ_VECT;
|
|
3'd2: vect <= `FIRQ_VECT;
|
|
default: vect <= `DBG_VECT | {nmi_i,firq_i,irq_i,1'b0};
|
|
endcase
|
|
end
|
else if (firq_i & !firqim & !sync_state) begin
|
else if (firq_i & !firqim & !sync_state) begin
|
bs_o <= 1'b1;
|
bs_o <= 1'b1;
|
ir[`LOBYTE] <= `INT;
|
ir[`LOBYTE] <= `INT;
|
ipg <= 2'b11;
|
ipg <= 2'b11;
|
vect <= `FIRQ_VECT;
|
vect <= `FIRQ_VECT;
|
| Line 1339... |
Line 1593... |
bs_o <= 1'b1;
|
bs_o <= 1'b1;
|
ir[`LOBYTE] <= `INT;
|
ir[`LOBYTE] <= `INT;
|
ipg <= 2'b11;
|
ipg <= 2'b11;
|
vect <= `IRQ_VECT;
|
vect <= `IRQ_VECT;
|
end
|
end
|
|
`ifdef SUPPORT_DEBUG_REG
|
|
// Check for instruction breakpoint hit.
|
|
else if (brkctrl[0].en && brkctrl[0].match_type==BMT_IA && (pc & {{20{1'b1}},brkctrl[0].amask})==brkad[0]) begin
|
|
brkctrl[0].hit <= 1'b1;
|
|
bs_o <= 1'b1;
|
|
ir[`LOBYTE] <= `INT;
|
|
ipg <= 2'b11;
|
|
vect <= `DBG_VECT;
|
|
end
|
|
else if (brkctrl[1].en && brkctrl[1].match_type==BMT_IA && (pc & {{20{1'b1}},brkctrl[1].amask})==brkad[1]) begin
|
|
brkctrl[1].hit <= 1'b1;
|
|
bs_o <= 1'b1;
|
|
ir[`LOBYTE] <= `INT;
|
|
ipg <= 2'b11;
|
|
vect <= `DBG_VECT;
|
|
end
|
|
else if (brkctrl[2].en && brkctrl[2].match_type==BMT_IA && (pc & {{20{1'b1}},brkctrl[2].amask})==brkad[2]) begin
|
|
brkctrl[2].hit <= 1'b1;
|
|
bs_o <= 1'b1;
|
|
ir[`LOBYTE] <= `INT;
|
|
ipg <= 2'b11;
|
|
vect <= `DBG_VECT;
|
|
end
|
|
else if (brkctrl[3].en && brkctrl[3].match_type==BMT_IA && (pc & {{20{1'b1}},brkctrl[3].amask})==brkad[3]) begin
|
|
brkctrl[3].hit <= 1'b1;
|
|
bs_o <= 1'b1;
|
|
ir[`LOBYTE] <= `INT;
|
|
ipg <= 2'b11;
|
|
vect <= `DBG_VECT;
|
|
end
|
|
`endif
|
else begin
|
else begin
|
if (sync_state) begin
|
if (sync_state) begin
|
ba_o <= 1'b1;
|
ba_o <= 1'b1;
|
next_state(IFETCH);
|
next_state(IFETCH);
|
end
|
end
|
| Line 1473... |
Line 1758... |
nf <= nf | ir[bitsPerByte+3];
|
nf <= nf | ir[bitsPerByte+3];
|
im <= im | ir[bitsPerByte+4];
|
im <= im | ir[bitsPerByte+4];
|
hf <= hf | ir[bitsPerByte+5];
|
hf <= hf | ir[bitsPerByte+5];
|
firqim <= firqim | ir[bitsPerByte+6];
|
firqim <= firqim | ir[bitsPerByte+6];
|
ef <= ef | ir[bitsPerByte+7];
|
ef <= ef | ir[bitsPerByte+7];
|
|
dm <= dm | ir[bitsPerByte+8];
|
pc <= pcp2;
|
pc <= pcp2;
|
end
|
end
|
`ANDCC:
|
`ANDCC:
|
begin
|
begin
|
cf <= cf & ir[bitsPerByte];
|
cf <= cf & ir[bitsPerByte];
|
| Line 1485... |
Line 1771... |
nf <= nf & ir[bitsPerByte+3];
|
nf <= nf & ir[bitsPerByte+3];
|
im <= im & ir[bitsPerByte+4];
|
im <= im & ir[bitsPerByte+4];
|
hf <= hf & ir[bitsPerByte+5];
|
hf <= hf & ir[bitsPerByte+5];
|
firqim <= firqim & ir[bitsPerByte+6];
|
firqim <= firqim & ir[bitsPerByte+6];
|
ef <= ef & ir[bitsPerByte+7];
|
ef <= ef & ir[bitsPerByte+7];
|
|
dm <= dm & ir[bitsPerByte+8];
|
pc <= pcp2;
|
pc <= pcp2;
|
end
|
end
|
`DAA:
|
`DAA:
|
begin
|
begin
|
if (hf || acca[3:0] > 4'd9)
|
if (hf || acca[3:0] > 4'd9)
|
| Line 1503... |
Line 1790... |
zf <= zf & ir[bitsPerByte+2];
|
zf <= zf & ir[bitsPerByte+2];
|
nf <= nf & ir[bitsPerByte+3];
|
nf <= nf & ir[bitsPerByte+3];
|
im <= im & ir[bitsPerByte+4];
|
im <= im & ir[bitsPerByte+4];
|
hf <= hf & ir[bitsPerByte+5];
|
hf <= hf & ir[bitsPerByte+5];
|
firqim <= firqim & ir[bitsPerByte+6];
|
firqim <= firqim & ir[bitsPerByte+6];
|
|
dm <= dm & ir[bitsPerByte+8];
|
ef <= 1'b1;
|
ef <= 1'b1;
|
pc <= pc + 2'd2;
|
pc <= pc + 2'd2;
|
ir[`HIBYTE] <= -1;
|
ir[`HIBYTE] <= -1;
|
isFar <= `TRUE;
|
isFar <= `TRUE;
|
wait_state <= `TRUE;
|
wait_state <= `TRUE;
|
next_state(PUSH1);
|
next_state(PUSH1);
|
end
|
end
|
`LDMD: begin
|
`LDMD: begin
|
natMd <= ir[bitsPerByte];
|
natMd <= ir[bitsPerByte];
|
firqMd <= ir[bitsPerByte+1];
|
firqMd <= ir[bitsPerByte+1];
|
|
iplMd <= ir[bitsPerByte+2];
|
|
pc <= pc + 2'd2;
|
|
end
|
|
`BITMD:
|
|
begin
|
|
res <= {dbz,iop,3'd0,iplMd,firqMd,natMd} & ir[`BYTE2];
|
|
if (ir[bitsPerByte+7])
|
|
dbz <= 1'b0;
|
|
if (ir[bitsPerByte+6])
|
|
iop <= 1'b0;
|
pc <= pc + 2'd2;
|
pc <= pc + 2'd2;
|
end
|
end
|
`TFR: pc <= pc + 2'd2;
|
`TFR: pc <= pc + 2'd2;
|
`EXG: pc <= pc + 2'd2;
|
`EXG: pc <= pc + 2'd2;
|
`ABX: res <= xr + accb;
|
`ABX: res <= xr + accb;
|
| Line 1525... |
Line 1823... |
`PG3: begin ipg <= 2'b10; ir <= ir[bitsPerByte*5-1:bitsPerByte]; next_state(DECODE); end
|
`PG3: begin ipg <= 2'b10; ir <= ir[bitsPerByte*5-1:bitsPerByte]; next_state(DECODE); end
|
`FAR: begin isFar <= `TRUE; ir <= ir[bitsPerByte*5-1:bitsPerByte]; next_state(DECODE); end
|
`FAR: begin isFar <= `TRUE; ir <= ir[bitsPerByte*5-1:bitsPerByte]; next_state(DECODE); end
|
`ifdef EIGHTBIT
|
`ifdef EIGHTBIT
|
`OUTER: begin isOuterIndexed <= `TRUE; ir <= ir[bitsPerByte*5-1:bitsPerByte]; next_state(DECODE); end
|
`OUTER: begin isOuterIndexed <= `TRUE; ir <= ir[bitsPerByte*5-1:bitsPerByte]; next_state(DECODE); end
|
`endif
|
`endif
|
`NEGA,`NEGB: begin res12 <= -acc[`LOBYTE]; a <= 24'h00; b <= acc; end
|
`NEGA,`NEGB:
|
|
if (dm) begin
|
|
a <= 'b0; b <= acc;
|
|
next_state(CALC);
|
|
end
|
|
else begin res12 <= -acc[`LOBYTE]; a <= 24'h00; b <= acc; end
|
`COMA,`COMB: begin res12 <= ~acc[`LOBYTE]; end
|
`COMA,`COMB: begin res12 <= ~acc[`LOBYTE]; end
|
`LSRA,`LSRB: begin res12 <= {acc[0],1'b0,acc[BPBM1:1]}; end
|
`LSRA,`LSRB: begin res12 <= {acc[0],1'b0,acc[BPBM1:1]}; end
|
`RORA,`RORB: begin res12 <= {acc[0],cf,acc[BPBM1:1]}; end
|
`RORA,`RORB: begin res12 <= {acc[0],cf,acc[BPBM1:1]}; end
|
`ASRA,`ASRB: begin res12 <= {acc[0],acc[BPBM1],acc[BPBM1:1]}; end
|
`ASRA,`ASRB: begin res12 <= {acc[0],acc[BPBM1],acc[BPBM1:1]}; end
|
`ASLA,`ASLB: begin res12 <= {acc[`LOBYTE],1'b0}; end
|
`ASLA,`ASLB: begin res12 <= {acc[`LOBYTE],1'b0}; end
|
`ROLA,`ROLB: begin res12 <= {acc[`LOBYTE],cf}; end
|
`ROLA,`ROLB: begin res12 <= {acc[`LOBYTE],cf}; end
|
`DECA,`DECB: begin res12 <= acc[`LOBYTE] - 2'd1; end
|
`DECA,`DECB: begin res12 <= acc[`LOBYTE] - 2'd1; end
|
`INCA,`INCB: begin res12 <= acc[`LOBYTE] + 2'd1; end
|
`INCA,`INCB: begin res12 <= acc[`LOBYTE] + 2'd1; end
|
`TSTA,`TSTB: begin res12 <= acc[`LOBYTE]; end
|
`TSTA,`TSTB: begin res12 <= acc[`LOBYTE]; end
|
`CLRA,`CLRB: begin res12 <= 13'h000; end
|
`CLRA,`CLRB: begin res12 <= 13'h000; end
|
|
`MUL: if (dm) begin divcnt <= 6'd17; next_state(MUL2); end
|
`ifdef SUPPORT_6309
|
`ifdef SUPPORT_6309
|
`TSTD: res <= {acca,accb};
|
`TSTD: res <= {acca,accb};
|
`TSTW: res <= {acce,accf};
|
`TSTW: res <= {acce,accf};
|
`TSTE: res12 <= acce;
|
`TSTE: res12 <= acce;
|
`TSTF: res12 <= accf;
|
`TSTF: res12 <= accf;
|
`NEGD: begin res <= -{acca,accb}; a <= 'd0; b <= {acca,accb}; end
|
`NEGD:
|
|
if (dm) begin
|
|
a <= 'd0; b <= {acca,accb};
|
|
next_state(CALC);
|
|
end
|
|
else begin res <= -{acca,accb}; a <= 'd0; b <= {acca,accb}; end
|
`INCE,`INCF: begin res12 <= acc[`LOBYTE] + 2'd1; end
|
`INCE,`INCF: begin res12 <= acc[`LOBYTE] + 2'd1; end
|
`INCD: res <= {acca,accb} + 2'd1;
|
`INCD: res <= {acca,accb} + 2'd1;
|
`INCW: res <= {acce,accf} + 2'd1;
|
`INCW: res <= {acce,accf} + 2'd1;
|
`DECE,`DECF: begin res12 <= acc[`LOBYTE] - 2'd1; end
|
`DECE,`DECF: begin res12 <= acc[`LOBYTE] - 2'd1; end
|
`DECD: res <= {acca,accb} - 2'd1;
|
`DECD: res <= {acca,accb} - 2'd1;
|
| Line 1592... |
Line 1901... |
nf <= sum12[3];
|
nf <= sum12[3];
|
im <= sum12[4];
|
im <= sum12[4];
|
hf <= sum12[5];
|
hf <= sum12[5];
|
firqim <= sum12[6];
|
firqim <= sum12[6];
|
ef <= sum12[7];
|
ef <= sum12[7];
|
|
dm <= sum12[8];
|
end
|
end
|
4'b1011: begin dpr <= sum12; nf <= sum12[bitsPerByte-1]; zf <= sum12[`LOBYTE]=='b0; cf <= sum12[bitsPerByte]; vf <= fnAddOverflow(src1[bitsPerByte-1],src2[bitsPerByte-1],sum12[bitsPerByte-1]); end
|
4'b1011: begin dpr <= sum12; nf <= sum12[bitsPerByte-1]; zf <= sum12[`LOBYTE]=='b0; cf <= sum12[bitsPerByte]; vf <= fnAddOverflow(src1[bitsPerByte-1],src2[bitsPerByte-1],sum12[bitsPerByte-1]); end
|
endcase
|
endcase
|
end
|
end
|
`ADCR:
|
`ADCR:
|
| Line 1617... |
Line 1927... |
nf <= sum12c[3];
|
nf <= sum12c[3];
|
im <= sum12c[4];
|
im <= sum12c[4];
|
hf <= sum12c[5];
|
hf <= sum12c[5];
|
firqim <= sum12c[6];
|
firqim <= sum12c[6];
|
ef <= sum12c[7];
|
ef <= sum12c[7];
|
|
dm <= sum12c[8];
|
end
|
end
|
4'b1011: begin dpr <= sum12c; nf <= sum12c[bitsPerByte-1]; zf <= sum12c[`LOBYTE]=='b0; cf <= sum12c[bitsPerByte]; vf <= fnAddOverflow(src1[bitsPerByte-1],src2[bitsPerByte-1],sum12c[bitsPerByte-1]); end
|
4'b1011: begin dpr <= sum12c; nf <= sum12c[bitsPerByte-1]; zf <= sum12c[`LOBYTE]=='b0; cf <= sum12c[bitsPerByte]; vf <= fnAddOverflow(src1[bitsPerByte-1],src2[bitsPerByte-1],sum12c[bitsPerByte-1]); end
|
endcase
|
endcase
|
end
|
end
|
`ANDR:
|
`ANDR:
|
| Line 1642... |
Line 1953... |
nf <= and12[3];
|
nf <= and12[3];
|
im <= and12[4];
|
im <= and12[4];
|
hf <= and12[5];
|
hf <= and12[5];
|
firqim <= and12[6];
|
firqim <= and12[6];
|
ef <= and12[7];
|
ef <= and12[7];
|
|
dm <= and12[8];
|
end
|
end
|
4'b1011: begin dpr <= and12; nf <= and12[bitsPerByte-1]; zf <= and12[`LOBYTE]=='b0; vf <= 1'b0; end
|
4'b1011: begin dpr <= and12; nf <= and12[bitsPerByte-1]; zf <= and12[`LOBYTE]=='b0; vf <= 1'b0; end
|
endcase
|
endcase
|
end
|
end
|
`EORR:
|
`EORR:
|
| Line 1667... |
Line 1979... |
nf <= eor12[3];
|
nf <= eor12[3];
|
im <= eor12[4];
|
im <= eor12[4];
|
hf <= eor12[5];
|
hf <= eor12[5];
|
firqim <= eor12[6];
|
firqim <= eor12[6];
|
ef <= eor12[7];
|
ef <= eor12[7];
|
|
dm <= eor12[8];
|
end
|
end
|
4'b1011: begin dpr <= eor12; nf <= eor12[bitsPerByte-1]; zf <= eor12[`LOBYTE]=='b0; vf <= 1'b0; end
|
4'b1011: begin dpr <= eor12; nf <= eor12[bitsPerByte-1]; zf <= eor12[`LOBYTE]=='b0; vf <= 1'b0; end
|
endcase
|
endcase
|
end
|
end
|
`ORR:
|
`ORR:
|
| Line 1692... |
Line 2005... |
nf <= or12[3];
|
nf <= or12[3];
|
im <= or12[4];
|
im <= or12[4];
|
hf <= or12[5];
|
hf <= or12[5];
|
firqim <= or12[6];
|
firqim <= or12[6];
|
ef <= or12[7];
|
ef <= or12[7];
|
|
dm <= or12[8];
|
end
|
end
|
4'b1011: begin dpr <= or12; nf <= or12[bitsPerByte-1]; zf <= or12[`LOBYTE]=='b0; vf <= 1'b0; end
|
4'b1011: begin dpr <= or12; nf <= or12[bitsPerByte-1]; zf <= or12[`LOBYTE]=='b0; vf <= 1'b0; end
|
endcase
|
endcase
|
end
|
end
|
`CMPR:
|
`CMPR:
|
| Line 1732... |
Line 2046... |
nf <= dif12c[3];
|
nf <= dif12c[3];
|
im <= dif12c[4];
|
im <= dif12c[4];
|
hf <= dif12c[5];
|
hf <= dif12c[5];
|
firqim <= dif12c[6];
|
firqim <= dif12c[6];
|
ef <= dif12c[7];
|
ef <= dif12c[7];
|
|
dm <= dif12c[8];
|
end
|
end
|
4'b1011: begin dpr <= dif12c; nf <= dif12c[bitsPerByte-1]; zf <= dif12c[`LOBYTE]=='b0; cf <= dif12c[bitsPerByte]; vf <= fnSubOverflow(src1[bitsPerByte-1],src2[bitsPerByte-1],dif12c[bitsPerByte-1]); end
|
4'b1011: begin dpr <= dif12c; nf <= dif12c[bitsPerByte-1]; zf <= dif12c[`LOBYTE]=='b0; cf <= dif12c[bitsPerByte]; vf <= fnSubOverflow(src1[bitsPerByte-1],src2[bitsPerByte-1],dif12c[bitsPerByte-1]); end
|
endcase
|
endcase
|
end
|
end
|
`SUBR:
|
`SUBR:
|
| Line 1757... |
Line 2072... |
nf <= dif12[3];
|
nf <= dif12[3];
|
im <= dif12[4];
|
im <= dif12[4];
|
hf <= dif12[5];
|
hf <= dif12[5];
|
firqim <= dif12[6];
|
firqim <= dif12[6];
|
ef <= dif12[7];
|
ef <= dif12[7];
|
|
dm <= dif12[8];
|
end
|
end
|
4'b1011: begin dpr <= dif12; nf <= dif12[bitsPerByte-1]; zf <= dif12[`LOBYTE]=='b0; cf <= dif12[bitsPerByte]; vf <= fnSubOverflow(src1[bitsPerByte-1],src2[bitsPerByte-1],dif12[bitsPerByte-1]); end
|
4'b1011: begin dpr <= dif12; nf <= dif12[bitsPerByte-1]; zf <= dif12[`LOBYTE]=='b0; cf <= dif12[bitsPerByte]; vf <= fnSubOverflow(src1[bitsPerByte-1],src2[bitsPerByte-1],dif12[bitsPerByte-1]); end
|
endcase
|
endcase
|
end
|
end
|
`endif
|
`endif
|
| Line 1770... |
Line 2086... |
`LDE_IMM,`LDF_IMM:
|
`LDE_IMM,`LDF_IMM:
|
begin res12 <= ir[`HIBYTE]; pc <= pc + 2'd2; end
|
begin res12 <= ir[`HIBYTE]; pc <= pc + 2'd2; end
|
`endif
|
`endif
|
// Immediate mode instructions
|
// Immediate mode instructions
|
`SUBA_IMM,`SUBB_IMM,`CMPA_IMM,`CMPB_IMM:
|
`SUBA_IMM,`SUBB_IMM,`CMPA_IMM,`CMPB_IMM:
|
begin res12 <= acc[`LOBYTE] - ir[`HIBYTE]; pc <= pc + 4'd2; a <= acc[`LOBYTE]; b <= ir[`HIBYTE]; end
|
if (dm) begin pc <= pc + 4'd2; a <= acc[`LOBYTE]; b <= ir[`HIBYTE]; next_state(CALC); end
|
|
else begin res12 <= acc[`LOBYTE] - ir[`HIBYTE]; pc <= pc + 4'd2; a <= acc[`LOBYTE]; b <= ir[`HIBYTE]; end
|
`SBCA_IMM,`SBCB_IMM:
|
`SBCA_IMM,`SBCB_IMM:
|
begin res12 <= acc[`LOBYTE] - ir[`HIBYTE] - cf; pc <= pc + 2'd2; a <= acc[`LOBYTE]; b <= ir[`HIBYTE]; end
|
if (dm) begin pc <= pc + 4'd2; a <= acc[`LOBYTE]; b <= ir[`HIBYTE]; next_state(CALC); end
|
|
else begin res12 <= acc[`LOBYTE] - ir[`HIBYTE] - cf; pc <= pc + 2'd2; a <= acc[`LOBYTE]; b <= ir[`HIBYTE]; end
|
`ANDA_IMM,`ANDB_IMM,`BITA_IMM,`BITB_IMM:
|
`ANDA_IMM,`ANDB_IMM,`BITA_IMM,`BITB_IMM:
|
begin res12 <= acc[`LOBYTE] & ir[`HIBYTE]; pc <= pc + 2'd2; a <= acc[`LOBYTE]; b <= ir[`HIBYTE]; end
|
begin res12 <= acc[`LOBYTE] & ir[`HIBYTE]; pc <= pc + 2'd2; a <= acc[`LOBYTE]; b <= ir[`HIBYTE]; end
|
`LDA_IMM,`LDB_IMM:
|
`LDA_IMM,`LDB_IMM:
|
begin res12 <= ir[`HIBYTE]; pc <= pc + 2'd2; end
|
begin res12 <= ir[`HIBYTE]; pc <= pc + 2'd2; end
|
`EORA_IMM,`EORB_IMM:
|
`EORA_IMM,`EORB_IMM:
|
begin res12 <= acc[`LOBYTE] ^ ir[`HIBYTE]; pc <= pc + 2'd2; a <= acc[`LOBYTE]; b <= ir[`HIBYTE]; end
|
begin res12 <= acc[`LOBYTE] ^ ir[`HIBYTE]; pc <= pc + 2'd2; a <= acc[`LOBYTE]; b <= ir[`HIBYTE]; end
|
`ADCA_IMM,`ADCB_IMM:
|
`ADCA_IMM,`ADCB_IMM:
|
begin res12 <= acc[`LOBYTE] + ir[`HIBYTE] + cf; pc <= pc + 2'd2; a <= acc[`LOBYTE]; b <= ir[`HIBYTE]; end
|
if (dm) begin pc <= pc + 4'd2; a <= acc[`LOBYTE]; b <= ir[`HIBYTE]; next_state(CALC); end
|
|
else begin res12 <= acc[`LOBYTE] + ir[`HIBYTE] + cf; pc <= pc + 2'd2; a <= acc[`LOBYTE]; b <= ir[`HIBYTE]; end
|
`ORA_IMM,`ORB_IMM:
|
`ORA_IMM,`ORB_IMM:
|
begin res12 <= acc[`LOBYTE] | ir[`HIBYTE]; pc <= pc + 2'd2; a <= acc[`LOBYTE]; b <= ir[`HIBYTE]; end
|
begin res12 <= acc[`LOBYTE] | ir[`HIBYTE]; pc <= pc + 2'd2; a <= acc[`LOBYTE]; b <= ir[`HIBYTE]; end
|
`ADDA_IMM,`ADDB_IMM:
|
`ADDA_IMM,`ADDB_IMM:
|
begin res12 <= acc[`LOBYTE] + ir[`HIBYTE]; pc <= pc + 2'd2; a <= acc[`LOBYTE]; b <= ir[`HIBYTE]; end
|
if (dm) begin pc <= pc + 4'd2; a <= acc[`LOBYTE]; b <= ir[`HIBYTE]; next_state(CALC); end
|
|
else begin res12 <= acc[`LOBYTE] + ir[`HIBYTE]; pc <= pc + 2'd2; a <= acc[`LOBYTE]; b <= ir[`HIBYTE]; end
|
`ifdef SUPPORT_6309
|
`ifdef SUPPORT_6309
|
`BITD_IMM,
|
`BITD_IMM,
|
`ANDD_IMM:
|
`ANDD_IMM:
|
begin
|
begin
|
res <= {acca[`LOBYTE],accb[`LOBYTE]} & {ir[`BYTE2],ir[`BYTE3]};
|
res <= {acca[`LOBYTE],accb[`LOBYTE]} & {ir[`BYTE2],ir[`BYTE3]};
|
| Line 1804... |
Line 2124... |
res <= {acca[`LOBYTE],accb[`LOBYTE]} | {ir[`BYTE2],ir[`BYTE3]};
|
res <= {acca[`LOBYTE],accb[`LOBYTE]} | {ir[`BYTE2],ir[`BYTE3]};
|
pc <= pc + 32'd3;
|
pc <= pc + 32'd3;
|
end
|
end
|
`endif
|
`endif
|
`ADDD_IMM:
|
`ADDD_IMM:
|
begin
|
if (dm) begin
|
|
a <= {acca,accb};
|
|
b <= {ir[`BYTE2],ir[`BYTE3]};
|
|
pc <= pc + 2'd3;
|
|
next_state(CALC);
|
|
end
|
|
else begin
|
res <= {acca[`LOBYTE],accb[`LOBYTE]} + {ir[`HIBYTE],ir[`BYTE3]};
|
res <= {acca[`LOBYTE],accb[`LOBYTE]} + {ir[`HIBYTE],ir[`BYTE3]};
|
pc <= pc + 2'd3;
|
pc <= pc + 2'd3;
|
end
|
end
|
`ifdef SUPPORT_6309
|
`ifdef SUPPORT_6309
|
`ADDW_IMM:
|
`ADDW_IMM:
|
begin
|
begin
|
res <= {acce[`LOBYTE],accf[`LOBYTE]} + {ir[`HIBYTE],ir[`BYTE3]};
|
res <= {acce[`LOBYTE],accf[`LOBYTE]} + {ir[`HIBYTE],ir[`BYTE3]};
|
pc <= pc + 2'd3;
|
pc <= pc + 2'd3;
|
end
|
end
|
`ADCD_IMM:
|
`ADCD_IMM:
|
begin
|
if (dm) begin
|
|
a <= {acca,accb};
|
|
b <= {ir[`BYTE2],ir[`BYTE3]};
|
|
pc <= pc + 32'd3;
|
|
next_state(CALC);
|
|
end
|
|
else begin
|
res <= {acca[`LOBYTE],accb[`LOBYTE]} + {ir[`BYTE2],ir[`BYTE3]} + {23'b0,cf};
|
res <= {acca[`LOBYTE],accb[`LOBYTE]} + {ir[`BYTE2],ir[`BYTE3]} + {23'b0,cf};
|
pc <= pc + 32'd3;
|
pc <= pc + 32'd3;
|
end
|
end
|
`endif
|
`endif
|
`SUBD_IMM:
|
`SUBD_IMM:
|
begin
|
if (dm) begin
|
|
a <= {acca,accb};
|
|
b <= {ir[`BYTE2],ir[`BYTE3]};
|
|
pc <= pc + 32'd3;
|
|
next_state(CALC);
|
|
end
|
|
else begin
|
res <= {acca[`LOBYTE],accb[`LOBYTE]} - {ir[`HIBYTE],ir[`BYTE3]};
|
res <= {acca[`LOBYTE],accb[`LOBYTE]} - {ir[`HIBYTE],ir[`BYTE3]};
|
pc <= pc + 2'd3;
|
pc <= pc + 2'd3;
|
end
|
end
|
`ifdef SUPPORT_6309
|
`ifdef SUPPORT_6309
|
`SUBW_IMM:
|
`SUBW_IMM:
|
begin
|
begin
|
res <= {acce[`LOBYTE],accf[`LOBYTE]} - {ir[`HIBYTE],ir[`BYTE3]};
|
res <= {acce[`LOBYTE],accf[`LOBYTE]} - {ir[`HIBYTE],ir[`BYTE3]};
|
pc <= pc + 2'd3;
|
pc <= pc + 2'd3;
|
end
|
end
|
`SBCD_IMM:
|
`SBCD_IMM:
|
begin
|
if (dm) begin
|
|
a <= {acca,accb};
|
|
b <= {ir[`BYTE2],ir[`BYTE3]};
|
|
pc <= pc + 32'd3;
|
|
next_state(CALC);
|
|
end
|
|
else begin
|
res <= {acca[`LOBYTE],accb[`LOBYTE]} - {ir[`BYTE2],ir[`BYTE3]} - {23'b0,cf};
|
res <= {acca[`LOBYTE],accb[`LOBYTE]} - {ir[`BYTE2],ir[`BYTE3]} - {23'b0,cf};
|
pc <= pc + 32'd3;
|
pc <= pc + 32'd3;
|
end
|
end
|
`LDW_IMM:
|
`LDW_IMM:
|
begin
|
begin
|
| Line 1854... |
Line 2198... |
res <= {ir[`HIBYTE],ir[`BYTE3]};
|
res <= {ir[`HIBYTE],ir[`BYTE3]};
|
pc <= pc + 2'd3;
|
pc <= pc + 2'd3;
|
end
|
end
|
|
|
`CMPD_IMM:
|
`CMPD_IMM:
|
begin
|
if (dm) begin
|
|
a <= {acca,accb};
|
|
b <= {ir[`BYTE2],ir[`BYTE3]};
|
|
pc <= pc + 32'd3;
|
|
next_state(CALC);
|
|
end
|
|
else begin
|
res <= {acca[`LOBYTE],accb[`LOBYTE]} - {ir[`HIBYTE],ir[`BYTE3]};
|
res <= {acca[`LOBYTE],accb[`LOBYTE]} - {ir[`HIBYTE],ir[`BYTE3]};
|
pc <= pc + 2'd3;
|
pc <= pc + 2'd3;
|
a <= {acca[`LOBYTE],accb[`LOBYTE]};
|
a <= {acca[`LOBYTE],accb[`LOBYTE]};
|
b <= {ir[`HIBYTE],ir[`BYTE3]};
|
b <= {ir[`HIBYTE],ir[`BYTE3]};
|
end
|
end
|
| Line 1907... |
Line 2257... |
radr <= dp_address;
|
radr <= dp_address;
|
pc <= pc + 2'd2;
|
pc <= pc + 2'd2;
|
next_state(LOAD1);
|
next_state(LOAD1);
|
end
|
end
|
`ifdef SUPPORT_6309
|
`ifdef SUPPORT_6309
|
|
`DIVD_IMM:
|
|
begin
|
|
b <= {ir[`BYTE3],ir[`BYTE2]};
|
|
pc <= pc + 2'd2;
|
|
next_state(DIV1);
|
|
end
|
|
`DIVQ_IMM:
|
|
begin
|
|
b <= {ir[`BYTE3],ir[`BYTE2]};
|
|
pc <= pc + 2'd3;
|
|
next_state(DIV1);
|
|
end
|
|
`MULD_IMM:
|
|
begin
|
|
b <= {ir[`BYTE3],ir[`BYTE2]};
|
|
pc <= pc + 2'd3;
|
|
divcnt <= 6'd7;
|
|
next_state(MUL2);
|
|
end
|
|
`endif
|
|
`ifdef SUPPORT_6309
|
`CMPE_DP,`CMPF_DP,
|
`CMPE_DP,`CMPF_DP,
|
`LDE_DP,`LDF_DP,
|
`LDE_DP,`LDF_DP,
|
`SUBE_DP,`SUBF_DP,
|
`SUBE_DP,`SUBF_DP,
|
`endif
|
`endif
|
`SUBA_DP,`CMPA_DP,`SBCA_DP,`ANDA_DP,`BITA_DP,`LDA_DP,`EORA_DP,`ADCA_DP,`ORA_DP,`ADDA_DP,
|
`SUBA_DP,`CMPA_DP,`SBCA_DP,`ANDA_DP,`BITA_DP,`LDA_DP,`EORA_DP,`ADCA_DP,`ORA_DP,`ADDA_DP,
|
| Line 1923... |
Line 2294... |
end
|
end
|
`ifdef SUPPORT_6309
|
`ifdef SUPPORT_6309
|
`BITD_DP,
|
`BITD_DP,
|
`ANDD_DP,
|
`ANDD_DP,
|
`ORD_DP,
|
`ORD_DP,
|
|
`DIVD_DP,
|
|
`DIVQ_DP,
|
`EORD_DP:
|
`EORD_DP:
|
begin
|
begin
|
load_what <= `LW_BL;
|
load_what <= `LW_BL;
|
radr <= dp_address;
|
radr <= dp_address;
|
pc <= pc + 2'd2;
|
pc <= pc + 2'd2;
|
next_state(LOAD1);
|
next_state(LOAD1);
|
end
|
end
|
`endif
|
`endif
|
`ifdef SUPPORT_6309
|
`ifdef SUPPORT_6309
|
|
`MULD_DP,
|
`ADDW_DP,`CMPW_DP,`LDW_DP,`SUBW_DP,
|
`ADDW_DP,`CMPW_DP,`LDW_DP,`SUBW_DP,
|
`endif
|
`endif
|
`SUBD_DP,`ADDD_DP,`LDD_DP,`CMPD_DP,`ADCD_DP,`SBCD_DP:
|
`SUBD_DP,`ADDD_DP,`LDD_DP,`CMPD_DP,`ADCD_DP,`SBCD_DP:
|
begin
|
begin
|
load_what <= `LW_BH;
|
load_what <= `LW_BH;
|
| Line 2009... |
Line 2383... |
end
|
end
|
`ifdef SUPPORT_6309
|
`ifdef SUPPORT_6309
|
`BITD_NDX,
|
`BITD_NDX,
|
`ANDD_NDX,
|
`ANDD_NDX,
|
`ORD_NDX,
|
`ORD_NDX,
|
|
`DIVD_NDX,
|
|
`DIVQ_NDX,
|
`EORD_NDX:
|
`EORD_NDX:
|
begin
|
begin
|
pc <= pc + insnsz;
|
pc <= pc + insnsz;
|
if (isIndirect) begin
|
if (isIndirect) begin
|
load_what <= isFar ? `LW_IA2316 : `LW_IAH;
|
load_what <= isFar ? `LW_IA2316 : `LW_IAH;
|
| Line 2025... |
Line 2401... |
load_what <= `LW_BL;
|
load_what <= `LW_BL;
|
radr <= NdxAddr;
|
radr <= NdxAddr;
|
next_state(LOAD1);
|
next_state(LOAD1);
|
end
|
end
|
end
|
end
|
|
`MULD_NDX:
|
|
begin
|
|
pc <= pc + insnsz;
|
|
if (isIndirect) begin
|
|
load_what <= isFar ? `LW_IA2316 : `LW_IAH;
|
|
load_what2 <= `LW_BH;
|
|
radr <= NdxAddr;
|
|
next_state(LOAD1);
|
|
end
|
|
else begin
|
|
b <= 24'd0;
|
|
load_what <= `LW_BH;
|
|
radr <= NdxAddr;
|
|
next_state(LOAD1);
|
|
end
|
|
end
|
`endif
|
`endif
|
`ifdef SUPPORT_6309
|
`ifdef SUPPORT_6309
|
`ADDW_NDX,`CMPW_NDX,`LDW_NDX,`SUBW_NDX,
|
`ADDW_NDX,`CMPW_NDX,`LDW_NDX,`SUBW_NDX,
|
`endif
|
`endif
|
`SUBD_NDX,`ADDD_NDX,`LDD_NDX,`CMPD_NDX,`ADCD_NDX,`SBCD_NDX:
|
`SUBD_NDX,`ADDD_NDX,`LDD_NDX,`CMPD_NDX,`ADCD_NDX,`SBCD_NDX:
|
| Line 2128... |
Line 2520... |
end
|
end
|
`ifdef SUPPORT_6309
|
`ifdef SUPPORT_6309
|
`BITD_EXT,
|
`BITD_EXT,
|
`ANDD_EXT,
|
`ANDD_EXT,
|
`ORD_EXT,
|
`ORD_EXT,
|
|
`DIVD_EXT,
|
|
`DIVQ_EXT,
|
`EORD_EXT:
|
`EORD_EXT:
|
begin
|
begin
|
load_what <= `LW_BL;
|
load_what <= `LW_BL;
|
radr <= ex_address;
|
radr <= ex_address;
|
pc <= pc + (isFar ? 32'd4 : 32'd3);
|
pc <= pc + (isFar ? 32'd4 : 32'd3);
|
next_state(LOAD1);
|
next_state(LOAD1);
|
end
|
end
|
`endif
|
`endif
|
`ifdef SUPPORT_6309
|
`ifdef SUPPORT_6309
|
|
`MULD_EXT,
|
`ADDW_EXT,`CMPW_EXT,`LDW_EXT,`SUBW_EXT,
|
`ADDW_EXT,`CMPW_EXT,`LDW_EXT,`SUBW_EXT,
|
`endif
|
`endif
|
`SUBD_EXT,`ADDD_EXT,`LDD_EXT,`CMPD_EXT,`ADCD_EXT,`SBCD_EXT:
|
`SUBD_EXT,`ADDD_EXT,`LDD_EXT,`CMPD_EXT,`ADCD_EXT,`SBCD_EXT:
|
begin
|
begin
|
load_what <= `LW_BH;
|
load_what <= `LW_BH;
|
| Line 2346... |
Line 2741... |
next_state(LOAD1);
|
next_state(LOAD1);
|
end
|
end
|
end
|
end
|
else begin
|
else begin
|
if (isNMI | isIRQ | isSWI | isSWI2 | isSWI3) begin
|
if (isNMI | isIRQ | isSWI | isSWI2 | isSWI3) begin
|
ir[`HIBYTE] <= 16'hFFFF;
|
ir[`HIBYTE] <= natMd ? 12'hFFF : 12'h0FF;
|
ef <= 1'b1;
|
ef <= 1'b1;
|
end
|
end
|
else if (isFIRQ) begin
|
else if (isFIRQ) begin
|
if (natMd) begin
|
if (natMd) begin
|
ef <= firqMd;
|
ef <= firqMd;
|
ir[`HIBYTE] <= firqMd ? 16'hFFFF : 12'h81;
|
ir[`HIBYTE] <= firqMd ? 12'hFFF : 12'h081;
|
end
|
end
|
else begin
|
else begin
|
ir[`HIBYTE] <= 12'h81;
|
ir[`HIBYTE] <= 12'h081;
|
ef <= 1'b0;
|
ef <= 1'b0;
|
end
|
end
|
end
|
end
|
pc <= pc;
|
pc <= pc;
|
isFar <= `TRUE;
|
isFar <= `TRUE;
|
next_state(PUSH1);
|
next_state(PUSH1);
|
end
|
end
|
end
|
end
|
default: ;
|
default:
|
|
if (natMd) begin
|
|
iop <= 1'b1;
|
|
bs_o <= 1'b1;
|
|
ir[`LOBYTE] <= `INT;
|
|
ipg <= 2'b11;
|
|
vect <= `IOP_VECT;
|
|
next_state(DECODE);
|
|
end
|
endcase
|
endcase
|
end
|
end
|
endtask
|
endtask
|
|
|
// ============================================================================
|
// ============================================================================
|
| Line 2378... |
Line 2781... |
begin
|
begin
|
`ifdef SUPPORT_DCACHE
|
`ifdef SUPPORT_DCACHE
|
if (unCachedData)
|
if (unCachedData)
|
`endif
|
`endif
|
case(radr)
|
case(radr)
|
{{BPB*3-8{1'b1}},8'hE0}: load_tsk({2'b0,id});
|
`CORENO: load_tsk({2'b0,id});
|
{{BPB*3-8{1'b1}},8'hE1}: load_tsk(chkpoint);
|
`CHKPOINT: load_tsk(chkpoint);
|
{{BPB*3-8{1'b1}},8'hE4}: load_tsk(12'h0);
|
`MSCOUNT+0: load_tsk(12'h0);
|
{{BPB*3-8{1'b1}},8'hE5}: load_tsk(ms_count[35:24]);
|
`MSCOUNT+1: load_tsk(ms_count[35:24]);
|
{{BPB*3-8{1'b1}},8'hE6}: load_tsk(ms_count[23:12]);
|
`MSCOUNT+2: load_tsk(ms_count[23:12]);
|
{{BPB*3-8{1'b1}},8'hE7}: load_tsk(ms_count[11: 0]);
|
`MSCOUNT+3: load_tsk(ms_count[11: 0]);
|
|
`ifdef SUPPORT_DEBUG_REG
|
|
`BRKAD0+0: load_tsk(brkad[0][`BYTE2]);
|
|
`BRKAD0+1: load_tsk(brkad[0][`BYTE1]);
|
|
`BRKAD1+0: load_tsk(brkad[1][`BYTE2]);
|
|
`BRKAD1+1: load_tsk(brkad[1][`BYTE1]);
|
|
`BRKAD2+0: load_tsk(brkad[2][`BYTE2]);
|
|
`BRKAD2+1: load_tsk(brkad[2][`BYTE1]);
|
|
`BRKAD3+0: load_tsk(brkad[3][`BYTE2]);
|
|
`BRKAD3+1: load_tsk(brkad[3][`BYTE1]);
|
|
`BRKCTRL0: load_tsk(brkctrl[0]);
|
|
`BRKCTRL1: load_tsk(brkctrl[1]);
|
|
`BRKCTRL2: load_tsk(brkctrl[2]);
|
|
`BRKCTRL3: load_tsk(brkctrl[3]);
|
|
`endif
|
default:
|
default:
|
|
`ifdef SUPPORT_DEBUG_REG
|
|
if (brkctrl[0].en && brkctrl[0].match_type==BMT_LS && (radr & {{20{1'b1}},brkctrl[0].amask})==brkad[0]) begin
|
|
brkctrl[0].hit <= 1'b1;
|
|
bs_o <= 1'b1;
|
|
ir[`LOBYTE] <= `INT;
|
|
ipg <= 2'b11;
|
|
vect <= `DBG_VECT;
|
|
next_state(DECODE);
|
|
end
|
|
else if (brkctrl[1].en && brkctrl[1].match_type==BMT_LS && (radr & {{20{1'b1}},brkctrl[1].amask})==brkad[1]) begin
|
|
brkctrl[1].hit <= 1'b1;
|
|
bs_o <= 1'b1;
|
|
ir[`LOBYTE] <= `INT;
|
|
ipg <= 2'b11;
|
|
vect <= `DBG_VECT;
|
|
next_state(DECODE);
|
|
end
|
|
else if (brkctrl[2].en && brkctrl[2].match_type==BMT_LS && (radr & {{20{1'b1}},brkctrl[2].amask})==brkad[2]) begin
|
|
brkctrl[2].hit <= 1'b1;
|
|
bs_o <= 1'b1;
|
|
ir[`LOBYTE] <= `INT;
|
|
ipg <= 2'b11;
|
|
vect <= `DBG_VECT;
|
|
next_state(DECODE);
|
|
end
|
|
else if (brkctrl[3].en && brkctrl[3].match_type==BMT_LS && (radr & {{20{1'b1}},brkctrl[3].amask})==brkad[3]) begin
|
|
brkctrl[3].hit <= 1'b1;
|
|
bs_o <= 1'b1;
|
|
ir[`LOBYTE] <= `INT;
|
|
ipg <= 2'b11;
|
|
vect <= `DBG_VECT;
|
|
next_state(DECODE);
|
|
end
|
|
else
|
|
`endif
|
if (~ack_i) begin
|
if (~ack_i) begin
|
lock_o <= lock_bus;
|
lock_o <= lock_bus;
|
wb_read(radr);
|
wb_read(radr);
|
if (!tsc)
|
if (!tsc)
|
next_state(LOAD2);
|
next_state(LOAD2);
|
| Line 2435... |
Line 2887... |
// ============================================================================
|
// ============================================================================
|
task tExecute;
|
task tExecute;
|
begin
|
begin
|
next_state(IFETCH);
|
next_state(IFETCH);
|
case(ir12)
|
case(ir12)
|
|
`SUBD_IMM,
|
`SUBD_DP,`SUBD_NDX,`SUBD_EXT,
|
`SUBD_DP,`SUBD_NDX,`SUBD_EXT,
|
`CMPD_DP,`CMPD_NDX,`CMPD_EXT:
|
`CMPD_DP,`CMPD_NDX,`CMPD_EXT:
|
begin
|
if (dm)
|
|
res <= bcdsubo;
|
|
else begin
|
a <= {acca[`LOBYTE],accb[`LOBYTE]};
|
a <= {acca[`LOBYTE],accb[`LOBYTE]};
|
res <= {acca[`LOBYTE],accb[`LOBYTE]} - b[`DBLBYTE];
|
res <= {acca[`LOBYTE],accb[`LOBYTE]} - b[`DBLBYTE];
|
end
|
end
|
`SBCD_DP,`SBCD_NDX,`SBCD_EXT:
|
`SBCD_IMM,`SBCD_DP,`SBCD_NDX,`SBCD_EXT:
|
begin
|
if (dm)
|
|
res <= bcdsubo;
|
|
else begin
|
a <= {acca[`LOBYTE],accb[`LOBYTE]};
|
a <= {acca[`LOBYTE],accb[`LOBYTE]};
|
res <= {acca[`LOBYTE],accb[`LOBYTE]} - b[`DBLBYTE] - {23'b0,cf};
|
res <= {acca[`LOBYTE],accb[`LOBYTE]} - b[`DBLBYTE] - {23'b0,cf};
|
end
|
end
|
`ADDD_DP,`ADDD_NDX,`ADDD_EXT:
|
`ADDD_IMM,`ADDD_DP,`ADDD_NDX,`ADDD_EXT:
|
begin
|
if (dm)
|
|
res <= bcdaddo;
|
|
else begin
|
a <= {acca[`LOBYTE],accb[`LOBYTE]};
|
a <= {acca[`LOBYTE],accb[`LOBYTE]};
|
res <= {acca[`LOBYTE],accb[`LOBYTE]} + b[`DBLBYTE];
|
res <= {acca[`LOBYTE],accb[`LOBYTE]} + b[`DBLBYTE];
|
end
|
end
|
`ifdef SUPPORT_6309
|
`ifdef SUPPORT_6309
|
`SUBW_DP,`SUBW_NDX,`SUBW_EXT,
|
`SUBW_DP,`SUBW_NDX,`SUBW_EXT,
|
| Line 2466... |
Line 2925... |
res <= {acce[`LOBYTE],accf[`LOBYTE]} + b[`DBLBYTE];
|
res <= {acce[`LOBYTE],accf[`LOBYTE]} + b[`DBLBYTE];
|
end
|
end
|
`LDW_DP,`LDW_NDX,`LDW_EXT:
|
`LDW_DP,`LDW_NDX,`LDW_EXT:
|
res <= b[`DBLBYTE];
|
res <= b[`DBLBYTE];
|
`endif
|
`endif
|
`ADCD_DP,`ADCD_NDX,`ADCD_EXT:
|
`ADCD_IMM,`ADCD_DP,`ADCD_NDX,`ADCD_EXT:
|
begin
|
if (dm)
|
|
res <= bcdaddo;
|
|
else begin
|
a <= {acca[`LOBYTE],accb[`LOBYTE]};
|
a <= {acca[`LOBYTE],accb[`LOBYTE]};
|
res <= {acca[`LOBYTE],accb[`LOBYTE]} + b[`DBLBYTE] + {23'b0,cf};
|
res <= {acca[`LOBYTE],accb[`LOBYTE]} + b[`DBLBYTE] + {23'b0,cf};
|
end
|
end
|
`LDD_DP,`LDD_NDX,`LDD_EXT:
|
`LDD_DP,`LDD_NDX,`LDD_EXT:
|
res <= b[`DBLBYTE];
|
res <= b[`DBLBYTE];
|
`ifdef SUPPORT_6309
|
`ifdef SUPPORT_6309
|
`CMPE_DP,`CMPE_NDX,`CMPE_EXT,
|
`CMPE_DP,`CMPE_NDX,`CMPE_EXT,
|
`CMPF_DP,`CMPF_NDX,`CMPF_EXT,
|
`CMPF_DP,`CMPF_NDX,`CMPF_EXT,
|
`SUBE_DP,`SUBE_NDX,`SUBE_EXT,
|
`SUBE_DP,`SUBE_NDX,`SUBE_EXT,
|
`SUBF_DP,`SUBF_NDX,`SUBF_EXT,
|
`SUBF_DP,`SUBF_NDX,`SUBF_EXT:
|
`endif
|
|
`CMPA_DP,`CMPA_NDX,`CMPA_EXT,
|
|
`SUBA_DP,`SUBA_NDX,`SUBA_EXT,
|
|
`CMPB_DP,`CMPB_NDX,`CMPB_EXT,
|
|
`SUBB_DP,`SUBB_NDX,`SUBB_EXT:
|
|
begin
|
begin
|
a <= acc;
|
a <= acc;
|
res12 <= acc[`LOBYTE] - b12;
|
res12 <= acc[`LOBYTE] - b12;
|
end
|
end
|
|
`endif
|
|
`CMPA_IMM,`CMPA_DP,`CMPA_NDX,`CMPA_EXT,
|
|
`SUBA_IMM,`SUBA_DP,`SUBA_NDX,`SUBA_EXT,
|
|
`CMPB_IMM,`CMPB_DP,`CMPB_NDX,`CMPB_EXT,
|
|
`SUBB_IMM,`SUBB_DP,`SUBB_NDX,`SUBB_EXT:
|
|
if (dm)
|
|
res12 <= bcdsubbo;
|
|
else begin
|
|
a <= acc;
|
|
res12 <= acc[`LOBYTE] - b12;
|
|
end
|
|
|
`SBCA_DP,`SBCA_NDX,`SBCA_EXT,
|
`SBCA_IMM,`SBCA_DP,`SBCA_NDX,`SBCA_EXT,
|
`SBCB_DP,`SBCB_NDX,`SBCB_EXT:
|
`SBCB_IMM,`SBCB_DP,`SBCB_NDX,`SBCB_EXT:
|
begin
|
if (dm)
|
|
res12 <= bcdsubbo;
|
|
else begin
|
a <= acc;
|
a <= acc;
|
res12 <= acc[`LOBYTE] - b12 - cf;
|
res12 <= acc[`LOBYTE] - b12 - cf;
|
end
|
end
|
`BITA_DP,`BITA_NDX,`BITA_EXT,
|
`BITA_DP,`BITA_NDX,`BITA_EXT,
|
`ANDA_DP,`ANDA_NDX,`ANDA_EXT,
|
`ANDA_DP,`ANDA_NDX,`ANDA_EXT,
|
| Line 2503... |
Line 2972... |
res12 <= acc[`LOBYTE] & b12;
|
res12 <= acc[`LOBYTE] & b12;
|
`ifdef SUPPORT_6309
|
`ifdef SUPPORT_6309
|
`BITD_DP,`BITD_NDX,`BITD_EXT,
|
`BITD_DP,`BITD_NDX,`BITD_EXT,
|
`ANDD_DP,`ANDD_NDX,`ANDD_EXT:
|
`ANDD_DP,`ANDD_NDX,`ANDD_EXT:
|
res <= {acca[`LOBYTE],accb[`LOBYTE]} & b[`DBLBYTE];
|
res <= {acca[`LOBYTE],accb[`LOBYTE]} & b[`DBLBYTE];
|
|
`DIVQ_DP,`DIVQ_NDX,`DIVQ_EXT,
|
|
`DIVD_DP,`DIVD_NDX,`DIVD_EXT:
|
|
if (b==24'd0) begin
|
|
dbz <= 1'b1;
|
|
bs_o <= 1'b1;
|
|
ir[`LOBYTE] <= `INT;
|
|
ipg <= 2'b11;
|
|
vect <= `IOP_VECT;
|
|
next_state(DECODE);
|
|
end
|
|
else
|
|
next_state(DIV1);
|
|
`MULD_DP,`MULD_NDX,`MULD_EXT:
|
|
begin
|
|
divcnt <= 6'd7;
|
|
next_state(MUL2);
|
|
end
|
`EORD_DP,`EORD_NDX,`EORD_EXT:
|
`EORD_DP,`EORD_NDX,`EORD_EXT:
|
res <= {acca[`LOBYTE],accb[`LOBYTE]} ^ b[`DBLBYTE];
|
res <= {acca[`LOBYTE],accb[`LOBYTE]} ^ b[`DBLBYTE];
|
`ORD_DP,`ORD_NDX,`ORD_EXT:
|
`ORD_DP,`ORD_NDX,`ORD_EXT:
|
res <= {acca[`LOBYTE],accb[`LOBYTE]} | b[`DBLBYTE];
|
res <= {acca[`LOBYTE],accb[`LOBYTE]} | b[`DBLBYTE];
|
`LDE_DP,`LDE_NDX,`LDE_EXT,
|
`LDE_DP,`LDE_NDX,`LDE_EXT,
|
| Line 2517... |
Line 3003... |
`LDB_DP,`LDB_NDX,`LDB_EXT:
|
`LDB_DP,`LDB_NDX,`LDB_EXT:
|
res12 <= b12;
|
res12 <= b12;
|
`EORA_DP,`EORA_NDX,`EORA_EXT,
|
`EORA_DP,`EORA_NDX,`EORA_EXT,
|
`EORB_DP,`EORB_NDX,`EORB_EXT:
|
`EORB_DP,`EORB_NDX,`EORB_EXT:
|
res12 <= acc[`LOBYTE] ^ b12;
|
res12 <= acc[`LOBYTE] ^ b12;
|
`ADCA_DP,`ADCA_NDX,`ADCA_EXT,
|
`ADCA_IMM,`ADCA_DP,`ADCA_NDX,`ADCA_EXT,
|
`ADCB_DP,`ADCB_NDX,`ADCB_EXT:
|
`ADCB_IMM,`ADCB_DP,`ADCB_NDX,`ADCB_EXT:
|
begin
|
if (dm)
|
|
res12 <= bcdaddbo;
|
|
else begin
|
a <= acc;
|
a <= acc;
|
res12 <= acc[`LOBYTE] + b12 + cf;
|
res12 <= acc[`LOBYTE] + b12 + cf;
|
end
|
end
|
`ORA_DP,`ORA_NDX,`ORA_EXT,
|
`ORA_DP,`ORA_NDX,`ORA_EXT,
|
`ORB_DP,`ORB_NDX,`ORB_EXT:
|
`ORB_DP,`ORB_NDX,`ORB_EXT:
|
res12 <= acc[`LOBYTE] | b12;
|
res12 <= acc[`LOBYTE] | b12;
|
`ifdef SUPPORT_6309
|
`ifdef SUPPORT_6309
|
`ADDE_DP,`ADDE_NDX,`ADDE_EXT,
|
`ADDE_DP,`ADDE_NDX,`ADDE_EXT,
|
`ADDF_DP,`ADDF_NDX,`ADDF_EXT,
|
`ADDF_DP,`ADDF_NDX,`ADDF_EXT,
|
`endif
|
`endif
|
`ADDA_DP,`ADDA_NDX,`ADDA_EXT,
|
`ADDA_IMM,`ADDA_DP,`ADDA_NDX,`ADDA_EXT,
|
`ADDB_DP,`ADDB_NDX,`ADDB_EXT:
|
`ADDB_IMM,`ADDB_DP,`ADDB_NDX,`ADDB_EXT:
|
begin
|
if (dm)
|
|
res12 <= bcdaddbo;
|
|
else begin
|
a <= acc;
|
a <= acc;
|
res12 <= acc[`LOBYTE] + b12;
|
res12 <= acc[`LOBYTE] + b12;
|
end
|
end
|
|
|
`LDU_DP,`LDS_DP,`LDX_DP,`LDY_DP,
|
`LDU_DP,`LDS_DP,`LDX_DP,`LDY_DP,
|
| Line 2546... |
Line 3036... |
`CMPY_DP,`CMPY_NDX,`CMPY_EXT: begin a <= yr; res <= yr[`DBLBYTE] - b[`DBLBYTE]; end
|
`CMPY_DP,`CMPY_NDX,`CMPY_EXT: begin a <= yr; res <= yr[`DBLBYTE] - b[`DBLBYTE]; end
|
`CMPS_DP,`CMPS_NDX,`CMPS_EXT: begin a <= ssp; res <= ssp[`DBLBYTE] - b[`DBLBYTE]; end
|
`CMPS_DP,`CMPS_NDX,`CMPS_EXT: begin a <= ssp; res <= ssp[`DBLBYTE] - b[`DBLBYTE]; end
|
`CMPU_DP,`CMPU_NDX,`CMPU_EXT: begin a <= usp; res <= usp[`DBLBYTE] - b[`DBLBYTE]; end
|
`CMPU_DP,`CMPU_NDX,`CMPU_EXT: begin a <= usp; res <= usp[`DBLBYTE] - b[`DBLBYTE]; end
|
|
|
`NEG_DP,`NEG_NDX,`NEG_EXT: begin res12 <= -b12; wadr <= radr; store_what <= `SW_RES8; next_state(STORE1); end
|
`NEG_DP,`NEG_NDX,`NEG_EXT: begin res12 <= -b12; wadr <= radr; store_what <= `SW_RES8; next_state(STORE1); end
|
|
`NEGA,`NEGB: begin res12 <= bcdnegbo; end
|
`COM_DP,`COM_NDX,`COM_EXT: begin res12 <= ~b12; wadr <= radr; store_what <= `SW_RES8; next_state(STORE1); end
|
`COM_DP,`COM_NDX,`COM_EXT: begin res12 <= ~b12; wadr <= radr; store_what <= `SW_RES8; next_state(STORE1); end
|
`LSR_DP,`LSR_NDX,`LSR_EXT: begin res12 <= {b[0],1'b0,b[BPBM1:1]}; store_what <= `SW_RES8; wadr <= radr; next_state(STORE1); end
|
`LSR_DP,`LSR_NDX,`LSR_EXT: begin res12 <= {b[0],1'b0,b[BPBM1:1]}; store_what <= `SW_RES8; wadr <= radr; next_state(STORE1); end
|
`ROR_DP,`ROR_NDX,`ROR_EXT: begin res12 <= {b[0],cf,b[BPBM1:1]}; store_what <= `SW_RES8; wadr <= radr; next_state(STORE1); end
|
`ROR_DP,`ROR_NDX,`ROR_EXT: begin res12 <= {b[0],cf,b[BPBM1:1]}; store_what <= `SW_RES8; wadr <= radr; next_state(STORE1); end
|
`ASR_DP,`ASR_NDX,`ASR_EXT: begin res12 <= {b[0],b[BPBM1],b[BPBM1:1]}; store_what <= `SW_RES8; wadr <= radr; next_state(STORE1); end
|
`ASR_DP,`ASR_NDX,`ASR_EXT: begin res12 <= {b[0],b[BPBM1],b[BPBM1:1]}; store_what <= `SW_RES8; wadr <= radr; next_state(STORE1); end
|
`ASL_DP,`ASL_NDX,`ASL_EXT: begin res12 <= {b12,1'b0}; wadr <= radr; store_what <= `SW_RES8; next_state(STORE1); end
|
`ASL_DP,`ASL_NDX,`ASL_EXT: begin res12 <= {b12,1'b0}; wadr <= radr; store_what <= `SW_RES8; next_state(STORE1); end
|
`ROL_DP,`ROL_NDX,`ROL_EXT: begin res12 <= {b12,cf}; wadr <= radr; store_what <= `SW_RES8; next_state(STORE1); end
|
`ROL_DP,`ROL_NDX,`ROL_EXT: begin res12 <= {b12,cf}; wadr <= radr; store_what <= `SW_RES8; next_state(STORE1); end
|
`DEC_DP,`DEC_NDX,`DEC_EXT: begin res12 <= b12 - 2'd1; wadr <= radr; store_what <= `SW_RES8; next_state(STORE1); end
|
`DEC_DP,`DEC_NDX,`DEC_EXT: begin res12 <= b12 - 2'd1; wadr <= radr; store_what <= `SW_RES8; next_state(STORE1); end
|
`INC_DP,`INC_NDX,`INC_EXT: begin res12 <= b12 + 2'd1; wadr <= radr; store_what <= `SW_RES8; next_state(STORE1); end
|
`INC_DP,`INC_NDX,`INC_EXT: begin res12 <= b12 + 2'd1; wadr <= radr; store_what <= `SW_RES8; next_state(STORE1); end
|
`TST_DP,`TST_NDX,`TST_EXT: res12 <= b12;
|
`TST_DP,`TST_NDX,`TST_EXT: res12 <= b12;
|
`ifdef SUPPORT_6309
|
`ifdef SUPPORT_6309
|
|
`NEGD: begin res <= bcdnego; end
|
`AIM_DP,`AIM_NDX,`AIM_EXT: begin res12 <= ir[`HIBYTE] & b12; wadr <= radr; store_what <= `SW_RES8; next_state(STORE1); end
|
`AIM_DP,`AIM_NDX,`AIM_EXT: begin res12 <= ir[`HIBYTE] & b12; wadr <= radr; store_what <= `SW_RES8; next_state(STORE1); end
|
`OIM_DP,`OIM_NDX,`OIM_EXT: begin res12 <= ir[`HIBYTE] | b12; wadr <= radr; store_what <= `SW_RES8; next_state(STORE1); end
|
`OIM_DP,`OIM_NDX,`OIM_EXT: begin res12 <= ir[`HIBYTE] | b12; wadr <= radr; store_what <= `SW_RES8; next_state(STORE1); end
|
`EIM_DP,`EIM_NDX,`OIM_EXT: begin res12 <= ir[`HIBYTE] ^ b12; wadr <= radr; store_what <= `SW_RES8; next_state(STORE1); end
|
`EIM_DP,`EIM_NDX,`OIM_EXT: begin res12 <= ir[`HIBYTE] ^ b12; wadr <= radr; store_what <= `SW_RES8; next_state(STORE1); end
|
`TIM_DP,`TIM_NDX,`TIM_EXT: begin res12 <= ir[`HIBYTE] & b12; end
|
`TIM_DP,`TIM_NDX,`TIM_EXT: begin res12 <= ir[`HIBYTE] & b12; end
|
`endif
|
`endif
|
| Line 2575... |
Line 3067... |
task tStore1;
|
task tStore1;
|
begin
|
begin
|
if (!ack_i) begin
|
if (!ack_i) begin
|
lock_o <= lock_bus;
|
lock_o <= lock_bus;
|
`ifdef SUPPORT_CHECKPOINT
|
`ifdef SUPPORT_CHECKPOINT
|
if (wadr=={{BPB*3-8{1'b1}},8'hE1})
|
if (wadr==CHKPOINT)
|
next_state(IFETCH);
|
next_state(IFETCH);
|
else
|
else
|
`endif
|
`endif
|
|
`ifdef SUPPORT_DEBUG_REG
|
|
if (brkctrl[0].en && brkctrl[0].match_type==BMT_DS && (radr & {{20{1'b1}},brkctrl[0].amask})==brkad[0]) begin
|
|
brkctrl[0].hit <= 1'b1;
|
|
bs_o <= 1'b1;
|
|
ir[`LOBYTE] <= `INT;
|
|
ipg <= 2'b11;
|
|
vect <= `DBG_VECT;
|
|
next_state(DECODE);
|
|
end
|
|
else if (brkctrl[1].en && brkctrl[1].match_type==BMT_DS && (radr & {{20{1'b1}},brkctrl[1].amask})==brkad[1]) begin
|
|
brkctrl[1].hit <= 1'b1;
|
|
bs_o <= 1'b1;
|
|
ir[`LOBYTE] <= `INT;
|
|
ipg <= 2'b11;
|
|
vect <= `DBG_VECT;
|
|
next_state(DECODE);
|
|
end
|
|
else if (brkctrl[2].en && brkctrl[2].match_type==BMT_DS && (radr & {{20{1'b1}},brkctrl[2].amask})==brkad[2]) begin
|
|
brkctrl[2].hit <= 1'b1;
|
|
bs_o <= 1'b1;
|
|
ir[`LOBYTE] <= `INT;
|
|
ipg <= 2'b11;
|
|
vect <= `DBG_VECT;
|
|
next_state(DECODE);
|
|
end
|
|
else if (brkctrl[3].en && brkctrl[3].match_type==BMT_DS && (radr & {{20{1'b1}},brkctrl[3].amask})==brkad[3]) begin
|
|
brkctrl[3].hit <= 1'b1;
|
|
bs_o <= 1'b1;
|
|
ir[`LOBYTE] <= `INT;
|
|
ipg <= 2'b11;
|
|
vect <= `DBG_VECT;
|
|
next_state(DECODE);
|
|
end
|
|
else
|
|
`endif
|
begin
|
begin
|
case(store_what)
|
case(store_what)
|
`SW_ACCDH: wb_write(wadr,acca[`LOBYTE]);
|
`SW_ACCDH: wb_write(wadr,acca[`LOBYTE]);
|
`SW_ACCDL: wb_write(wadr,accb[`LOBYTE]);
|
`SW_ACCDL: wb_write(wadr,accb[`LOBYTE]);
|
`SW_ACCA: wb_write(wadr,acca[`LOBYTE]);
|
`SW_ACCA: wb_write(wadr,acca[`LOBYTE]);
|
| Line 2798... |
Line 3325... |
case(ir12)
|
case(ir12)
|
`ABX: xr <= res;
|
`ABX: xr <= res;
|
`ADDA_IMM,`ADDA_DP,`ADDA_NDX,`ADDA_EXT,
|
`ADDA_IMM,`ADDA_DP,`ADDA_NDX,`ADDA_EXT,
|
`ADCA_IMM,`ADCA_DP,`ADCA_NDX,`ADCA_EXT:
|
`ADCA_IMM,`ADCA_DP,`ADCA_NDX,`ADCA_EXT:
|
begin
|
begin
|
cf <= (a[BPBM1]&b[BPBM1])|(a[BPBM1]&~res12[BPBM1])|(b[BPBM1]&~res12[BPBM1]);
|
cf <= dm ? bcdaddbcf : (a[BPBM1]&b[BPBM1])|(a[BPBM1]&~res12[BPBM1])|(b[BPBM1]&~res12[BPBM1]);
|
hf <= (a[`HCBIT]&b[`HCBIT])|(a[`HCBIT]&~res12[`HCBIT])|(b[`HCBIT]&~res12[`HCBIT]);
|
hf <= (a[`HCBIT]&b[`HCBIT])|(a[`HCBIT]&~res12[`HCBIT])|(b[`HCBIT]&~res12[`HCBIT]);
|
vf <= (res12[BPBM1] ^ b[BPBM1]) & (1'b1 ^ a[BPBM1] ^ b[BPBM1]);
|
vf <= (res12[BPBM1] ^ b[BPBM1]) & (1'b1 ^ a[BPBM1] ^ b[BPBM1]);
|
nf <= res12[BPBM1];
|
nf <= res12[BPBM1];
|
zf <= res12[`LOBYTE]==12'h000;
|
zf <= res12[`LOBYTE]==12'h000;
|
acca <= res12[`LOBYTE];
|
acca <= res12[`LOBYTE];
|
end
|
end
|
`ADDB_IMM,`ADDB_DP,`ADDB_NDX,`ADDB_EXT,
|
`ADDB_IMM,`ADDB_DP,`ADDB_NDX,`ADDB_EXT,
|
`ADCB_IMM,`ADCB_DP,`ADCB_NDX,`ADCB_EXT:
|
`ADCB_IMM,`ADCB_DP,`ADCB_NDX,`ADCB_EXT:
|
begin
|
begin
|
cf <= (a[BPBM1]&b[BPBM1])|(a[BPBM1]&~res12[BPBM1])|(b[BPBM1]&~res12[BPBM1]);
|
cf <= dm ? bcdaddbcf : (a[BPBM1]&b[BPBM1])|(a[BPBM1]&~res12[BPBM1])|(b[BPBM1]&~res12[BPBM1]);
|
hf <= (a[`HCBIT]&b[`HCBIT])|(a[`HCBIT]&~res12[`HCBIT])|(b[`HCBIT]&~res12[`HCBIT]);
|
hf <= (a[`HCBIT]&b[`HCBIT])|(a[`HCBIT]&~res12[`HCBIT])|(b[`HCBIT]&~res12[`HCBIT]);
|
vf <= (res12[BPBM1] ^ b[BPBM1]) & (1'b1 ^ a[BPBM1] ^ b[BPBM1]);
|
vf <= (res12[BPBM1] ^ b[BPBM1]) & (1'b1 ^ a[BPBM1] ^ b[BPBM1]);
|
nf <= res12[BPBM1];
|
nf <= res12[BPBM1];
|
zf <= res12[`LOBYTE]==12'h000;
|
zf <= res12[`LOBYTE]==12'h000;
|
accb <= res12[`LOBYTE];
|
accb <= res12[`LOBYTE];
|
| Line 2837... |
Line 3364... |
acce <= res12[`LOBYTE];
|
acce <= res12[`LOBYTE];
|
end
|
end
|
`endif
|
`endif
|
`ADDD_IMM,`ADDD_DP,`ADDD_NDX,`ADDD_EXT:
|
`ADDD_IMM,`ADDD_DP,`ADDD_NDX,`ADDD_EXT:
|
begin
|
begin
|
cf <= (a[BPBX2M1]&b[BPBX2M1])|(a[BPBX2M1]&~res[BPBX2M1])|(b[BPBX2M1]&~res[BPBX2M1]);
|
cf <= dm ? bcdaddcf : (a[BPBX2M1]&b[BPBX2M1])|(a[BPBX2M1]&~res[BPBX2M1])|(b[BPBX2M1]&~res[BPBX2M1]);
|
vf <= (res[BPBX2M1] ^ b[BPBX2M1]) & (1'b1 ^ a[BPBX2M1] ^ b[BPBX2M1]);
|
vf <= (res[BPBX2M1] ^ b[BPBX2M1]) & (1'b1 ^ a[BPBX2M1] ^ b[BPBX2M1]);
|
nf <= res[BPBX2M1];
|
nf <= res[BPBX2M1];
|
zf <= res[`DBLBYTE]==24'h000000;
|
zf <= res[`DBLBYTE]==24'h000000;
|
acca <= res[`HIBYTE];
|
acca <= res[`HIBYTE];
|
accb <= res[`LOBYTE];
|
accb <= res[`LOBYTE];
|
| Line 2856... |
Line 3383... |
acce <= res[`HIBYTE];
|
acce <= res[`HIBYTE];
|
accf <= res[`LOBYTE];
|
accf <= res[`LOBYTE];
|
end
|
end
|
`ADCD_IMM,`ADCD_DP,`ADCD_NDX,`ADCD_EXT:
|
`ADCD_IMM,`ADCD_DP,`ADCD_NDX,`ADCD_EXT:
|
begin
|
begin
|
cf <= (a[BPBX2M1]&b[BPBX2M1])|(a[BPBX2M1]&~res[BPBX2M1])|(b[BPBX2M1]&~res[BPBX2M1]);
|
cf <= dm ? bcdaddcf : (a[BPBX2M1]&b[BPBX2M1])|(a[BPBX2M1]&~res[BPBX2M1])|(b[BPBX2M1]&~res[BPBX2M1]);
|
vf <= (res[BPBX2M1] ^ b[BPBX2M1]) & (1'b1 ^ a[BPBX2M1] ^ b[BPBX2M1]);
|
vf <= (res[BPBX2M1] ^ b[BPBX2M1]) & (1'b1 ^ a[BPBX2M1] ^ b[BPBX2M1]);
|
nf <= res[BPBX2M1];
|
nf <= res[BPBX2M1];
|
zf <= res[`DBLBYTE]==24'h0000;
|
zf <= res[`DBLBYTE]==24'h0000;
|
acca <= res[`HIBYTE];
|
acca <= res[`HIBYTE];
|
accb <= res[`LOBYTE];
|
accb <= res[`LOBYTE];
|
| Line 2904... |
Line 3431... |
begin
|
begin
|
nf <= res24n;
|
nf <= res24n;
|
zf <= res24z;
|
zf <= res24z;
|
vf <= 1'b0;
|
vf <= 1'b0;
|
end
|
end
|
|
`DIVD_IMM,`DIVD_DP,`DIVD_NDX,`DIVD_EXT:
|
|
begin
|
|
acca <= res[`BYTE2];
|
|
accb <= res[`BYTE1];
|
|
// Overflow set eariler
|
|
cf <= res[0];
|
|
nf <= res[bitsPerByte-1];
|
|
zf <= ~|res[bitsPerByte-1:0];
|
|
end
|
|
`DIVQ_IMM,`DIVQ_DP,`DIVQ_NDX,`DIVQ_EXT:
|
|
begin
|
|
if (bitsPerByte==12) begin
|
|
acce <= divrem24[`BYTE2];
|
|
accf <= divrem24[`BYTE1];
|
|
acca <= divres48[`BYTE2];
|
|
accb <= divres48[`BYTE1];
|
|
// Overflow set eariler
|
|
cf <= divres48[0];
|
|
vf <= divres48[47:24]!={24{divres48[23]}};
|
|
nf <= divres48[23];
|
|
zf <= ~|divres48[23:0];
|
|
end
|
|
else if (bitsPerByte==8) begin
|
|
acce <= divrem16[`BYTE2];
|
|
accf <= divrem16[`BYTE1];
|
|
acca <= divres32[`BYTE2];
|
|
accb <= divres32[`BYTE1];
|
|
// Overflow set eariler
|
|
cf <= divres32[0];
|
|
vf <= divres32[31:16]!={16{divres32[15]}};
|
|
nf <= divres48[15];
|
|
zf <= ~|divres48[15:0];
|
|
end
|
|
end
|
|
`MULD_IMM,`MULD_DP,`MULD_NDX,`MULD_EXT:
|
|
begin
|
|
accb <= muld_res6[`BYTE1];
|
|
acca <= muld_res6[`BYTE2];
|
|
accf <= muld_res6[`BYTE3];
|
|
acce <= muld_res6[`BYTE4];
|
|
zf <= ~|muld_res6;
|
|
nf <= muld_res6[bitsPerByte*4-1];
|
|
end
|
`endif
|
`endif
|
`ASLA:
|
`ASLA:
|
begin
|
begin
|
cf <= res12c;
|
cf <= res12c;
|
hf <= (a[`HCBIT]&b[`HCBIT])|(a[`HCBIT]&~res12[`HCBIT])|(b[`HCBIT]&~res12[`HCBIT]);
|
hf <= (a[`HCBIT]&b[`HCBIT])|(a[`HCBIT]&~res12[`HCBIT])|(b[`HCBIT]&~res12[`HCBIT]);
|
| Line 3025... |
Line 3595... |
nf <= 1'b0;
|
nf <= 1'b0;
|
zf <= 1'b1;
|
zf <= 1'b1;
|
accb <= 12'h000;
|
accb <= 12'h000;
|
end
|
end
|
`ifdef SUPPORT_6309
|
`ifdef SUPPORT_6309
|
|
`BITMD:
|
|
zf <= res12==12'h0;
|
`CLRD:
|
`CLRD:
|
begin
|
begin
|
vf <= 1'b0;
|
vf <= 1'b0;
|
cf <= 1'b0;
|
cf <= 1'b0;
|
nf <= 1'b0;
|
nf <= 1'b0;
|
| Line 3069... |
Line 3641... |
nf <= 1'b0;
|
nf <= 1'b0;
|
zf <= 1'b1;
|
zf <= 1'b1;
|
end
|
end
|
`ifdef SUPPORT_6309
|
`ifdef SUPPORT_6309
|
`CMPE_IMM,`CMPE_DP,`CMPE_NDX,`CMPE_EXT,
|
`CMPE_IMM,`CMPE_DP,`CMPE_NDX,`CMPE_EXT,
|
`CMPF_IMM,`CMPF_DP,`CMPF_NDX,`CMPF_EXT,
|
`CMPF_IMM,`CMPF_DP,`CMPF_NDX,`CMPF_EXT:
|
|
begin
|
|
cf <= (~a[BPBM1]&b[BPBM1])|(res12[BPBM1]&~a[BPBM1])|(res12[BPBM1]&b[BPBM1]);
|
|
hf <= (~a[`HCBIT]&b[`HCBIT])|(res12[`HCBIT]&~a[`HCBIT])|(res12[`HCBIT]&b[`HCBIT]);
|
|
vf <= (1'b1 ^ res12[BPBM1] ^ b[BPBM1]) & (a[BPBM1] ^ b[BPBM1]);
|
|
nf <= res12[BPBM1];
|
|
zf <= res12[`LOBYTE]==12'h000;
|
|
end
|
`endif
|
`endif
|
`CMPA_IMM,`CMPA_DP,`CMPA_NDX,`CMPA_EXT,
|
`CMPA_IMM,`CMPA_DP,`CMPA_NDX,`CMPA_EXT,
|
`CMPB_IMM,`CMPB_DP,`CMPB_NDX,`CMPB_EXT:
|
`CMPB_IMM,`CMPB_DP,`CMPB_NDX,`CMPB_EXT:
|
begin
|
begin
|
cf <= (~a[BPBM1]&b[BPBM1])|(res12[BPBM1]&~a[BPBM1])|(res12[BPBM1]&b[BPBM1]);
|
cf <= dm ? bcdsubbcf : (~a[BPBM1]&b[BPBM1])|(res12[BPBM1]&~a[BPBM1])|(res12[BPBM1]&b[BPBM1]);
|
hf <= (~a[`HCBIT]&b[`HCBIT])|(res12[`HCBIT]&~a[`HCBIT])|(res12[`HCBIT]&b[`HCBIT]);
|
hf <= (~a[`HCBIT]&b[`HCBIT])|(res12[`HCBIT]&~a[`HCBIT])|(res12[`HCBIT]&b[`HCBIT]);
|
vf <= (1'b1 ^ res12[BPBM1] ^ b[BPBM1]) & (a[BPBM1] ^ b[BPBM1]);
|
vf <= (1'b1 ^ res12[BPBM1] ^ b[BPBM1]) & (a[BPBM1] ^ b[BPBM1]);
|
nf <= res12[BPBM1];
|
nf <= res12[BPBM1];
|
zf <= res12[`LOBYTE]==12'h000;
|
zf <= res12[`LOBYTE]==12'h000;
|
end
|
end
|
`ifdef SUPPORT_6309
|
`ifdef SUPPORT_6309
|
`CMPW_IMM,`CMPW_DP,`CMPW_NDX,`CMPW_EXT,
|
`CMPW_IMM,`CMPW_DP,`CMPW_NDX,`CMPW_EXT:
|
|
begin
|
|
cf <= (~a[BPBX2M1]&b[BPBX2M1])|(res[BPBX2M1]&~a[BPBX2M1])|(res[BPBX2M1]&b[BPBX2M1]);
|
|
vf <= (1'b1 ^ res[BPBX2M1] ^ b[BPBX2M1]) & (a[BPBX2M1] ^ b[BPBX2M1]);
|
|
nf <= res[BPBX2M1];
|
|
zf <= res[`DBLBYTE]==24'h000000;
|
|
end
|
`endif
|
`endif
|
`CMPD_IMM,`CMPD_DP,`CMPD_NDX,`CMPD_EXT:
|
`CMPD_IMM,`CMPD_DP,`CMPD_NDX,`CMPD_EXT:
|
begin
|
begin
|
cf <= (~a[BPBX2M1]&b[BPBX2M1])|(res[BPBX2M1]&~a[BPBX2M1])|(res[BPBX2M1]&b[BPBX2M1]);
|
cf <= dm ? bcdsubcf : (~a[BPBX2M1]&b[BPBX2M1])|(res[BPBX2M1]&~a[BPBX2M1])|(res[BPBX2M1]&b[BPBX2M1]);
|
vf <= (1'b1 ^ res[BPBX2M1] ^ b[BPBX2M1]) & (a[BPBX2M1] ^ b[BPBX2M1]);
|
vf <= (1'b1 ^ res[BPBX2M1] ^ b[BPBX2M1]) & (a[BPBX2M1] ^ b[BPBX2M1]);
|
nf <= res[BPBX2M1];
|
nf <= res[BPBX2M1];
|
zf <= res[`DBLBYTE]==24'h000000;
|
zf <= res[`DBLBYTE]==24'h000000;
|
end
|
end
|
`CMPS_IMM,`CMPS_DP,`CMPS_NDX,`CMPS_EXT,
|
`CMPS_IMM,`CMPS_DP,`CMPS_NDX,`CMPS_EXT,
|
| Line 3256... |
Line 3841... |
nf <= src1[3];
|
nf <= src1[3];
|
im <= src1[4];
|
im <= src1[4];
|
hf <= src1[5];
|
hf <= src1[5];
|
firqim <= src1[6];
|
firqim <= src1[6];
|
ef <= src1[7];
|
ef <= src1[7];
|
|
dm <= src1[8];
|
end
|
end
|
4'b1011: dpr <= src1[`LOBYTE];
|
4'b1011: dpr <= src1[`LOBYTE];
|
4'b1100: usppg <= src1[`DBLBYTE];
|
4'b1100: usppg <= src1[`DBLBYTE];
|
`ifdef SUPPORT_6309
|
`ifdef SUPPORT_6309
|
4'b0110: {acce,accf} <= src1[`DBLBYTE];
|
4'b0110: {acce,accf} <= src1[`DBLBYTE];
|
| Line 3292... |
Line 3878... |
nf <= src2[3];
|
nf <= src2[3];
|
im <= src2[4];
|
im <= src2[4];
|
hf <= src2[5];
|
hf <= src2[5];
|
firqim <= src2[6];
|
firqim <= src2[6];
|
ef <= src2[7];
|
ef <= src2[7];
|
|
dm <= src2[8];
|
end
|
end
|
4'b1011: dpr <= src2[`LOBYTE];
|
4'b1011: dpr <= src2[`LOBYTE];
|
4'b1100: usppg <= src2[`DBLBYTE];
|
4'b1100: usppg <= src2[`DBLBYTE];
|
`ifdef SUPPORT_6309
|
`ifdef SUPPORT_6309
|
4'b1110: acce <= src2[`LOBYTE];
|
4'b1110: acce <= src2[`LOBYTE];
|
| Line 3465... |
Line 4052... |
cf <= res12c;
|
cf <= res12c;
|
nf <= res12[BPBM1];
|
nf <= res12[BPBM1];
|
zf <= res12[`LOBYTE]==12'h000;
|
zf <= res12[`LOBYTE]==12'h000;
|
end
|
end
|
`MUL:
|
`MUL:
|
begin
|
if (dm) begin
|
|
accb <= bcdmul_res16[`BYTE1];
|
|
acca <= bcdmul_res16[`BYTE2];
|
|
zf <= ~|bcdmul_res16;
|
|
cf <= bcdmul_res16[bitsPerByte*2-1];
|
|
end
|
|
else begin
|
cf <= prod[BPBM1];
|
cf <= prod[BPBM1];
|
zf <= res24z;
|
zf <= res24z;
|
acca <= prod[`HIBYTE];
|
acca <= prod[`HIBYTE];
|
accb <= prod[`LOBYTE];
|
accb <= prod[`LOBYTE];
|
end
|
end
|
`NEGA:
|
`NEGA:
|
begin
|
begin
|
cf <= (~a[BPBM1]&b[BPBM1])|(res12[BPBM1]&~a[BPBM1])|(res12[BPBM1]&b[BPBM1]);
|
cf <= dm ? bcdnegbcf : (~a[BPBM1]&b[BPBM1])|(res12[BPBM1]&~a[BPBM1])|(res12[BPBM1]&b[BPBM1]);
|
hf <= (~a[`HCBIT]&b[`HCBIT])|(res12[`HCBIT]&~a[`HCBIT])|(res12[`HCBIT]&b[`HCBIT]);
|
hf <= (~a[`HCBIT]&b[`HCBIT])|(res12[`HCBIT]&~a[`HCBIT])|(res12[`HCBIT]&b[`HCBIT]);
|
vf <= (1'b1 ^ res12[BPBM1] ^ b[BPBM1]) & (a[BPBM1] ^ b[BPBM1]);
|
vf <= (1'b1 ^ res12[BPBM1] ^ b[BPBM1]) & (a[BPBM1] ^ b[BPBM1]);
|
nf <= res12[BPBM1];
|
nf <= res12[BPBM1];
|
zf <= res12[`LOBYTE]==12'h000;
|
zf <= res12[`LOBYTE]==12'h000;
|
acca <= res12[`LOBYTE];
|
acca <= res12[`LOBYTE];
|
end
|
end
|
`NEGB:
|
`NEGB:
|
begin
|
begin
|
cf <= (~a[BPBM1]&b[BPBM1])|(res12[BPBM1]&~a[BPBM1])|(res12[BPBM1]&b[BPBM1]);
|
cf <= dm ? bcdnegbcf : (~a[BPBM1]&b[BPBM1])|(res12[BPBM1]&~a[BPBM1])|(res12[BPBM1]&b[BPBM1]);
|
hf <= (~a[`HCBIT]&b[`HCBIT])|(res12[`HCBIT]&~a[`HCBIT])|(res12[`HCBIT]&b[`HCBIT]);
|
hf <= (~a[`HCBIT]&b[`HCBIT])|(res12[`HCBIT]&~a[`HCBIT])|(res12[`HCBIT]&b[`HCBIT]);
|
vf <= (1'b1 ^ res12[BPBM1] ^ b[BPBM1]) & (a[BPBM1] ^ b[BPBM1]);
|
vf <= (1'b1 ^ res12[BPBM1] ^ b[BPBM1]) & (a[BPBM1] ^ b[BPBM1]);
|
nf <= res12[BPBM1];
|
nf <= res12[BPBM1];
|
zf <= res12[`LOBYTE]==12'h000;
|
zf <= res12[`LOBYTE]==12'h000;
|
accb <= res12[`LOBYTE];
|
accb <= res12[`LOBYTE];
|
end
|
end
|
`ifdef SUPPORT_6309
|
`ifdef SUPPORT_6309
|
`NEGD:
|
`NEGD:
|
begin
|
begin
|
cf <= (~a[bitsPerByte*2-1]&b[bitsPerByte*2-1])|(res[bitsPerByte*2-1]&~a[bitsPerByte*2-1])|(res[bitsPerByte*2-1]&b[bitsPerByte*2-1]);
|
cf <= dm ? bcdnegcf : (~a[bitsPerByte*2-1]&b[bitsPerByte*2-1])|(res[bitsPerByte*2-1]&~a[bitsPerByte*2-1])|(res[bitsPerByte*2-1]&b[bitsPerByte*2-1]);
|
hf <= (~a[`HCBIT]&b[`HCBIT])|(res[`HCBIT]&~a[`HCBIT])|(res[`HCBIT]&b[`HCBIT]);
|
hf <= (~a[`HCBIT]&b[`HCBIT])|(res[`HCBIT]&~a[`HCBIT])|(res[`HCBIT]&b[`HCBIT]);
|
vf <= (1'b1 ^ res[bitsPerByte*2-1] ^ b[bitsPerByte*2-1]) & (a[bitsPerByte*2-1] ^ b[bitsPerByte*2-1]);
|
vf <= (1'b1 ^ res[bitsPerByte*2-1] ^ b[bitsPerByte*2-1]) & (a[bitsPerByte*2-1] ^ b[bitsPerByte*2-1]);
|
nf <= res[bitsPerByte*2-1];
|
nf <= res[bitsPerByte*2-1];
|
zf <= res[`DBLBYTE]=='h0;
|
zf <= res[`DBLBYTE]=='h0;
|
{acca,accb} <= res;
|
{acca,accb} <= res;
|
| Line 3556... |
Line 4149... |
nf <= res12[BPBM1];
|
nf <= res12[BPBM1];
|
zf <= res12[`LOBYTE]==12'h000;
|
zf <= res12[`LOBYTE]==12'h000;
|
end
|
end
|
`SBCA_IMM,`SBCA_DP,`SBCA_NDX,`SBCA_EXT:
|
`SBCA_IMM,`SBCA_DP,`SBCA_NDX,`SBCA_EXT:
|
begin
|
begin
|
cf <= (~a[BPBM1]&b[BPBM1])|(res12[BPBM1]&~a[BPBM1])|(res12[BPBM1]&b[BPBM1]);
|
cf <= dm ? bcdsubbcf : (~a[BPBM1]&b[BPBM1])|(res12[BPBM1]&~a[BPBM1])|(res12[BPBM1]&b[BPBM1]);
|
hf <= (~a[`HCBIT]&b[`HCBIT])|(res12[`HCBIT]&~a[`HCBIT])|(res12[`HCBIT]&b[`HCBIT]);
|
hf <= (~a[`HCBIT]&b[`HCBIT])|(res12[`HCBIT]&~a[`HCBIT])|(res12[`HCBIT]&b[`HCBIT]);
|
vf <= (1'b1 ^ res12[BPBM1] ^ b[BPBM1]) & (a[BPBM1] ^ b[BPBM1]);
|
vf <= (1'b1 ^ res12[BPBM1] ^ b[BPBM1]) & (a[BPBM1] ^ b[BPBM1]);
|
nf <= res12[BPBM1];
|
nf <= res12[BPBM1];
|
zf <= res12[`LOBYTE]==12'h000;
|
zf <= res12[`LOBYTE]==12'h000;
|
acca <= res12[`LOBYTE];
|
acca <= res12[`LOBYTE];
|
end
|
end
|
`SBCB_IMM,`SBCB_DP,`SBCB_NDX,`SBCB_EXT:
|
`SBCB_IMM,`SBCB_DP,`SBCB_NDX,`SBCB_EXT:
|
begin
|
begin
|
cf <= (~a[BPBM1]&b[BPBM1])|(res12[BPBM1]&~a[BPBM1])|(res12[BPBM1]&b[BPBM1]);
|
cf <= dm ? bcdsubbcf : (~a[BPBM1]&b[BPBM1])|(res12[BPBM1]&~a[BPBM1])|(res12[BPBM1]&b[BPBM1]);
|
hf <= (~a[`HCBIT]&b[`HCBIT])|(res12[`HCBIT]&~a[`HCBIT])|(res12[`HCBIT]&b[`HCBIT]);
|
hf <= (~a[`HCBIT]&b[`HCBIT])|(res12[`HCBIT]&~a[`HCBIT])|(res12[`HCBIT]&b[`HCBIT]);
|
vf <= (1'b1 ^ res12[BPBM1] ^ b[BPBM1]) & (a[BPBM1] ^ b[BPBM1]);
|
vf <= (1'b1 ^ res12[BPBM1] ^ b[BPBM1]) & (a[BPBM1] ^ b[BPBM1]);
|
nf <= res12[BPBM1];
|
nf <= res12[BPBM1];
|
zf <= res12[`LOBYTE]==12'h000;
|
zf <= res12[`LOBYTE]==12'h000;
|
accb <= res12[`LOBYTE];
|
accb <= res12[`LOBYTE];
|
| Line 3627... |
Line 4220... |
nf <= src1[3];
|
nf <= src1[3];
|
im <= src1[4];
|
im <= src1[4];
|
hf <= src1[5];
|
hf <= src1[5];
|
firqim <= src1[6];
|
firqim <= src1[6];
|
ef <= src1[7];
|
ef <= src1[7];
|
|
dm <= src1[8];
|
end
|
end
|
4'b1011: dpr <= src1[`LOBYTE];
|
4'b1011: dpr <= src1[`LOBYTE];
|
4'b1100: usppg <= src1[`DBLBYTE];
|
4'b1100: usppg <= src1[`DBLBYTE];
|
`ifdef SUPPORT_6309
|
`ifdef SUPPORT_6309
|
4'b0110: {acce,accf} <= src1[`DBLBYTE];
|
4'b0110: {acce,accf} <= src1[`DBLBYTE];
|
| Line 3674... |
Line 4268... |
begin
|
begin
|
acca <= res12[`LOBYTE];
|
acca <= res12[`LOBYTE];
|
nf <= res12n;
|
nf <= res12n;
|
zf <= res12z;
|
zf <= res12z;
|
vf <= (1'b1 ^ res12[BPBM1] ^ b[BPBM1]) & (a[BPBM1] ^ b[BPBM1]);
|
vf <= (1'b1 ^ res12[BPBM1] ^ b[BPBM1]) & (a[BPBM1] ^ b[BPBM1]);
|
cf <= res12c;
|
cf <= dm ? bcdsubbcf : res12c;
|
hf <= (~a[`HCBIT]&b[`HCBIT])|(res12[`HCBIT]&~a[`HCBIT])|(res12[`HCBIT]&b[`HCBIT]);
|
hf <= (~a[`HCBIT]&b[`HCBIT])|(res12[`HCBIT]&~a[`HCBIT])|(res12[`HCBIT]&b[`HCBIT]);
|
end
|
end
|
`SUBB_IMM,`SUBB_DP,`SUBB_NDX,`SUBB_EXT:
|
`SUBB_IMM,`SUBB_DP,`SUBB_NDX,`SUBB_EXT:
|
begin
|
begin
|
accb <= res12[`LOBYTE];
|
accb <= res12[`LOBYTE];
|
nf <= res12n;
|
nf <= res12n;
|
zf <= res12z;
|
zf <= res12z;
|
vf <= (1'b1 ^ res12[BPBM1] ^ b[BPBM1]) & (a[BPBM1] ^ b[BPBM1]);
|
vf <= (1'b1 ^ res12[BPBM1] ^ b[BPBM1]) & (a[BPBM1] ^ b[BPBM1]);
|
cf <= res12c;
|
cf <= dm ? bcdsubbcf : res12c;
|
hf <= (~a[`HCBIT]&b[`HCBIT])|(res12[`HCBIT]&~a[`HCBIT])|(res12[`HCBIT]&b[`HCBIT]);
|
hf <= (~a[`HCBIT]&b[`HCBIT])|(res12[`HCBIT]&~a[`HCBIT])|(res12[`HCBIT]&b[`HCBIT]);
|
end
|
end
|
`ifdef SUPPORT_6309
|
`ifdef SUPPORT_6309
|
`SUBE_IMM,`SUBE_DP,`SUBE_NDX,`SUBE_EXT:
|
`SUBE_IMM,`SUBE_DP,`SUBE_NDX,`SUBE_EXT:
|
begin
|
begin
|
| Line 3718... |
Line 4312... |
end
|
end
|
`SBCD_IMM,`SBCD_DP,`SBCD_NDX,`SBCD_EXT,
|
`SBCD_IMM,`SBCD_DP,`SBCD_NDX,`SBCD_EXT,
|
`endif
|
`endif
|
`SUBD_IMM,`SUBD_DP,`SUBD_NDX,`SUBD_EXT:
|
`SUBD_IMM,`SUBD_DP,`SUBD_NDX,`SUBD_EXT:
|
begin
|
begin
|
cf <= res24c;
|
cf <= dm ? bcdsubcf : res24c;
|
vf <= (1'b1 ^ res[BPBX2M1] ^ b[BPBX2M1]) & (a[BPBX2M1] ^ b[BPBX2M1]);
|
vf <= (1'b1 ^ res[BPBX2M1] ^ b[BPBX2M1]) & (a[BPBX2M1] ^ b[BPBX2M1]);
|
nf <= res[BPBX2M1];
|
nf <= res[BPBX2M1];
|
zf <= res[`DBLBYTE]==24'h000000;
|
zf <= res[`DBLBYTE]==24'h000000;
|
acca <= res[`HIBYTE];
|
acca <= res[`HIBYTE];
|
accb <= res[`LOBYTE];
|
accb <= res[`LOBYTE];
|
| Line 3802... |
Line 4396... |
adr_o <= adr;
|
adr_o <= adr;
|
end
|
end
|
end
|
end
|
endtask
|
endtask
|
|
|
|
// Trap writes to special registers
|
task wb_write;
|
task wb_write;
|
input [`TRPBYTE] adr;
|
input [`TRPBYTE] adr;
|
input [`LOBYTE] dat;
|
input [`LOBYTE] dat;
|
begin
|
begin
|
if (!tsc) begin
|
if (!tsc) begin
|
|
next_state(IFETCH);
|
|
`ifdef SUPPORT_DEBUG_REG
|
|
case(adr)
|
|
`BRKAD0+0: brkad[0][`BYTE2] <= dat;
|
|
`BRKAD0+1: brkad[0][`BYTE1] <= dat;
|
|
`BRKAD1+0: brkad[1][`BYTE2] <= dat;
|
|
`BRKAD1+1: brkad[1][`BYTE1] <= dat;
|
|
`BRKAD2+0: brkad[2][`BYTE2] <= dat;
|
|
`BRKAD2+1: brkad[2][`BYTE1] <= dat;
|
|
`BRKAD3+0: brkad[3][`BYTE2] <= dat;
|
|
`BRKAD3+1: brkad[3][`BYTE1] <= dat;
|
|
`BRKCTRL0: brkctrl[0] <= dat;
|
|
`BRKCTRL1: brkctrl[1] <= dat;
|
|
`BRKCTRL2: brkctrl[2] <= dat;
|
|
`BRKCTRL3: brkctrl[3] <= dat;
|
|
default:
|
|
begin
|
|
`endif
|
we_o <= 1'b1;
|
we_o <= 1'b1;
|
adr_o <= adr;
|
adr_o <= adr;
|
dat_o <= dat;
|
dat_o <= dat;
|
|
next_state(STORE1a);
|
|
`ifdef SUPPORT_DEBUG_REG
|
|
end
|
|
endcase
|
|
`endif
|
end
|
end
|
end
|
end
|
endtask
|
endtask
|
|
|
task wb_nack;
|
task wb_nack;
|
| Line 3855... |
Line 4473... |
nf <= dat[3];
|
nf <= dat[3];
|
im <= dat[4];
|
im <= dat[4];
|
hf <= dat[5];
|
hf <= dat[5];
|
firqim <= dat[6];
|
firqim <= dat[6];
|
ef <= dat[7];
|
ef <= dat[7];
|
|
dm <= dat[8];
|
if (isRTI) begin
|
if (isRTI) begin
|
$display("loaded ccr=%b", dat);
|
$display("loaded ccr=%b", dat);
|
ir[`HIBYTE] <= dat[7] ? 12'hFE : 12'h80;
|
ir[`HIBYTE] <= dat[7] ? 12'h3FE : 12'h080;
|
ssp <= ssp + 2'd1;
|
ssp <= ssp + 2'd1;
|
end
|
end
|
else if (isPULS)
|
else if (isPULS)
|
ssp <= ssp + 2'd1;
|
ssp <= ssp + 2'd1;
|
else if (isPULU)
|
else if (isPULU)
|
