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--
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-- Risc5x
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-- www.OpenCores.Org - November 2001
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--
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--
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-- This library is free software; you can distribute it and/or modify it
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-- under the terms of the GNU Lesser General Public License as published
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-- by the Free Software Foundation; either version 2.1 of the License, or
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-- (at your option) any later version.
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--
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-- This library is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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-- See the GNU Lesser General Public License for more details.
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--
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-- A RISC CPU core.
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--
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-- (c) Mike Johnson 2001. All Rights Reserved.
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-- mikej@opencores.org for support or any other issues.
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--
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-- Revision list
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--
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-- version 1.1 bug fix: Used wrong bank select bits in direct addressing mode
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-- INDF register returns 0 when indirectly read
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-- FSR bit 8 always set
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-- (cpu.vhd file changed)
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--
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-- version 1.0 initial opencores release
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--
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Risc5x is a small RISC CPU written in VHDL that is compatible with the 12 bit
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opcode PIC family. Single cycle operation normally, two cycles when the program
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counter is modified. Clock speeds of over 40Mhz are possible when using the
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Xilinx Virtex optimisations.
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Legal Stuff
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This core is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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You are responsible for any legal issues arising from the use of this core.
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The source files may be used and distributed without restriction provided that
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all copyright statements are not removed from the files and that any derivative
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work contains the original copyright notices and the associated disclaimer.
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PIC is a trademark of Microchip Technology Inc.
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Features
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The core has a single pipeline stage and is run from a single clock, so
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(ignoring program counter changes) a 40Mhz clock will give 40 MIPS processing
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speed. Any instruction which modifies the program counter, for example a branch
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or skip, will result in a pipeline stall and this will only cost one additional
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clock cycle.
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The CPU architecture chosen is not particularly FPGA friendly, for example
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multiplexers are generally quite expensive. The maximum combinatorial path delay
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is also long, so to ease the place and route tool's job the core is written at a
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low level. It instantiates a number of library macros, for example a 4:1 mux.
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Two versions of these are given, one is generic VHDL and the second is optimised
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for Xilinx Virtex series (including sparten2's etc). A constraints file locates
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the data path macros within the device and ensures an easy fit and high clock
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speed.
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Performance & Size
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The core builds to around 110 Virtex CLBS (depending on synthesis).
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>33 Mhz in a Virtex e - 6
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>40 Mhz in a Virtex e - 8
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There's some good free tools out there including a compiler, simulator and
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assembler (gusim & guasm for example).
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Synthesis & File description :
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Read the files in the following order.
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** PACKAGES **
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pkg_xilinx_prims.vhd (package containing low level Virtex blocks)
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only required if using Virtex optimised macros)
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pkg_prims.vhd (package containing macro components)
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pkg_risc5x.vhd (package containing some useful functions)
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** MACROS / RTL MODELS **
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mux8.vhd (8 to 1 muxer)
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mux4.vhd (4 to 1 muxer)
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mux2.vhd (2 to 1 muxer)
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mux2_add_reg.vhd (load or +1, used for program counter)
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alubit.vhd (ALU bit functions)
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add_sub.vhd (add or subtract)
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IMPORTANT : Each of the macros has TWO ARCHITECTURES, the first (VIRTEX) is for
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Virtex series devices ONLY, including Virtex, Virtexe, Sparten2, Sparten2e etc.
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The second (RTL) is generic VHDL, and is surrounded by synthesis directives :
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--pragma translate_off
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--pragma translate_on
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This makes the synthesis tool ignores the second architecture, but the simulator
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does not, resulting in optimal synthesis and fast simulation.
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If you do not wish to target Virtex series devices, YOU MUST remove the --pragma
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directives, and (optionally) delete the VIRTEX architecture.
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A PROBLEM : Some of the macros have generic attributes passed to them to define
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bus width etc. Unfortunately when the same macro is used twice with different
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generics some synthesis tools do not build a second copy of the macro. The
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easiest way round this is to generate EDIF's for each macro that is required,
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and then save it with the 'expected name'.
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For example if the Xilinx tools say they cannot find a mux4_9_0_FALSE then
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you would edit the default generics in mux4.vhd to
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entity MUX4 is
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generic (
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WIDTH : in natural := 9;
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SLICE : in natural := 0; -- 1 left, 0 right
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OP_REG : in boolean := FALSE
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);
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port (
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and build it to mux4_9_0_false.edf.
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You may need to build the files with *'s below :
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MUX2_8_1_FALSE.edf default so ok
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MUX2_7_1_FALSE.edf *
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MUX4_8_1_FALSE.edf default so ok
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MUX4_8_0_FALSE.edf *
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MUX4_9_0_FALSE.edf *
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MUX4_11_0_FALSE.edf *
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MUX8_8_FALSE.edf default so ok
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ADD_SUB_8.edf default so ok
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ALUBIT_8.edf default so ok
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MUX2_ADD_REG_11.edf default so ok
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If you are using Exemplar then you can analyze the whole lot and it gets it
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correct. The following works fine :
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analyze mux2_add_reg.vhd
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analyze mux2.vhd
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analyze mux4.vhd
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analyze mux8.vhd
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analyze add_sub.vhd
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analyze alubit.vhd
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analyze idec.vhd
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analyze alu.vhd
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analyze regs.vhd
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analyze cpu.vhd
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analyze risc5x_xil.vhd
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elaborate risc5x_xil
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** CORE **
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alu.vhd (ALU block)
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idec.vhd (instruction decode)
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regs.vhd (register file)
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cpu.vhd (CPU top level)
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regs.vhd also has two architectures, one optimised for Virtex and a generic one
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as well. The generic version has a simulation model of a dual port ram,
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which should be replaced be a synthesizable block.
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** TOP LEVELS **
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risc5x_xil.vhd (xilinx chip complete with program ram)
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OR
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cpu_tb.vhd (simulation model which loads a .hex program file)
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** OTHER **
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risc5x_xil.ucf (xilinx constraints file)
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jumptest.asm (sanity test program)
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jumptest.hex (sanity test binary)
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risc5x_xil.VHD is a synthesizable top level that instantiates some Xilinx block
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rams. For simulation replace risc5x_xil.vhd with cpu_tb.vhd which has extra
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debug.
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Signal inst_string in cpu_tb shows the current instruction being
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executed, and pc_t1 the address it came from. (t1 signifies one clock later than
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the PC, due to the delay through the program memory)
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Any questions or interest in customisation /locked / other cores (16x8x?) etc
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feel free to mail.
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mikej@opencores.org
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Cheers
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Mike.
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