OpenCores
URL https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk

Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [debugger/] [src/] [cpu_fnc_plugin/] [riscv-ext-a.cpp] - Diff between revs 2 and 4

Show entire file | Details | Blame | View Log

Rev 2 Rev 4
Line 5... Line 5...
 * @brief      RISC-V extension-A (Atomic Instructions).
 * @brief      RISC-V extension-A (Atomic Instructions).
 */
 */
 
 
#include "api_utils.h"
#include "api_utils.h"
#include "riscv-isa.h"
#include "riscv-isa.h"
#include "instructions.h"
#include "cpu_riscv_func.h"
 
 
namespace debugger {
namespace debugger {
 
 
 
void CpuRiver_Functional::addIsaExtensionA() {
void addIsaExtensionA(CpuContextType *data, AttributeType *out) {
 
    // TODO
    // TODO
    /*
    /*
    addInstr("AMOADD_W",           "00000????????????010?????0101111", NULL, out);
    addInstr("AMOADD_W",           "00000????????????010?????0101111", NULL, out);
    addInstr("AMOXOR_W",           "00100????????????010?????0101111", NULL, out);
    addInstr("AMOXOR_W",           "00100????????????010?????0101111", NULL, out);
    addInstr("AMOOR_W",            "01000????????????010?????0101111", NULL, out);
    addInstr("AMOOR_W",            "01000????????????010?????0101111", NULL, out);
Line 36... Line 35...
    addInstr("AMOMAXU_D",          "11100????????????011?????0101111", NULL, out);
    addInstr("AMOMAXU_D",          "11100????????????011?????0101111", NULL, out);
    addInstr("AMOSWAP_D",          "00001????????????011?????0101111", NULL, out);
    addInstr("AMOSWAP_D",          "00001????????????011?????0101111", NULL, out);
    addInstr("LR_D",               "00010??00000?????011?????0101111", NULL, out);
    addInstr("LR_D",               "00010??00000?????011?????0101111", NULL, out);
    addInstr("SC_D",               "00011????????????011?????0101111", NULL, out);
    addInstr("SC_D",               "00011????????????011?????0101111", NULL, out);
    */
    */
    data->csr[CSR_misa] |= (1LL << ('A' - 'A'));
    uint64_t isa = portCSR_.read(CSR_misa).val;
 
    portCSR_.write(CSR_misa, isa | (1LL << ('A' - 'A')));
}
}
 
 
}  // namespace debugger
}  // namespace debugger
 
 
 No newline at end of file
 No newline at end of file

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.