OpenCores
URL https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk

Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [debugger/] [src/] [cpu_sysc_plugin/] [riverlib/] [core/] [csr.cpp] - Diff between revs 2 and 4

Show entire file | Details | Blame | View Log

Rev 2 Rev 4
Line 1... Line 1...
/**
/*
 * @file
 *  Copyright 2018 Sergey Khabarov, sergeykhbr@gmail.com
 * @copyright  Copyright 2016 GNSS Sensor Ltd. All right reserved.
 *
 * @author     Sergey Khabarov - sergeykhbr@gmail.com
 *  Licensed under the Apache License, Version 2.0 (the "License");
 * @brief      CSR registers module.
 *  you may not use this file except in compliance with the License.
 
 *  You may obtain a copy of the License at
 
 *
 
 *      http://www.apache.org/licenses/LICENSE-2.0
 
 *
 
 *  Unless required by applicable law or agreed to in writing, software
 
 *  distributed under the License is distributed on an "AS IS" BASIS,
 
 *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 
 *  See the License for the specific language governing permissions and
 
 *  limitations under the License.
 */
 */
 
 
#include "csr.h"
#include "csr.h"
#include "riscv-isa.h"
#include "riscv-isa.h"
 
 
Line 77... Line 86...
         */
         */
        (*ordata)(RISCV_ARCH-1, RISCV_ARCH-2) = 2;
        (*ordata)(RISCV_ARCH-1, RISCV_ARCH-2) = 2;
        /** BitCharacterDescription
        /** BitCharacterDescription
         * 0  A Atomic extension
         * 0  A Atomic extension
         * 1  B Tentatively reserved for Bit operations extension
         * 1  B Tentatively reserved for Bit operations extension
         * 2  C Compressed extension3DDouble-precision Foating-point extension
         * 2  C Compressed extension
         * 4  E RV32E base ISA
         * 3  D Double-precision Foating-point extension
 
         * 4  E RV32E base ISA (embedded)
         * 5  F Single-precision Foating-point extension
         * 5  F Single-precision Foating-point extension
         * 6  G Additional standard extensions present
         * 6  G Additional standard extensions present
         * 7  H Hypervisor mode implemented
         * 7  H Hypervisor mode implemented
         * 8  I RV32I/64I/128I base ISA
         * 8  I RV32I/64I/128I base ISA
         * 9  J Reserved
         * 9  J Reserved
Line 105... Line 115...
         */
         */
        //(*ordata)['A' - 'A'] = 1;
        //(*ordata)['A' - 'A'] = 1;
        (*ordata)['I' - 'A'] = 1;
        (*ordata)['I' - 'A'] = 1;
        (*ordata)['M' - 'A'] = 1;
        (*ordata)['M' - 'A'] = 1;
        (*ordata)['U' - 'A'] = 1;
        (*ordata)['U' - 'A'] = 1;
 
        (*ordata)['C' - 'A'] = 1;
        break;
        break;
    case CSR_mvendorid:
    case CSR_mvendorid:
        break;
        break;
    case CSR_marchid:
    case CSR_marchid:
        break;
        break;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.