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URL https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk

Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [debugger/] [src/] [socsim_plugin/] [rfctrl.cpp] - Diff between revs 2 and 4

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Rev 2 Rev 4
Line 10... Line 10...
 
 
namespace debugger {
namespace debugger {
 
 
RfController::RfController(const char *name)  : IService(name) {
RfController::RfController(const char *name)  : IService(name) {
    registerInterface(static_cast<IMemoryOperation *>(this));
    registerInterface(static_cast<IMemoryOperation *>(this));
    registerAttribute("BaseAddress", &baseAddress_);
 
    registerAttribute("Length", &length_);
 
 
 
    baseAddress_.make_uint64(0);
 
    length_.make_uint64(0);
 
 
 
    memset(&regs_, 0, sizeof(regs_));
    memset(&regs_, 0, sizeof(regs_));
}
}
 
 
RfController::~RfController() {
RfController::~RfController() {
}
}
 
 
void RfController::postinitService() {
void RfController::postinitService() {
}
}
 
 
void RfController::b_transport(Axi4TransactionType *trans) {
ETransStatus RfController::b_transport(Axi4TransactionType *trans) {
    uint64_t mask = (length_.to_uint64() - 1);
    uint64_t mask = (length_.to_uint64() - 1);
    uint64_t off = ((trans->addr - getBaseAddress()) & mask) / 4;
    uint64_t off = ((trans->addr - getBaseAddress()) & mask) / 4;
    trans->response = MemResp_Valid;
    trans->response = MemResp_Valid;
    if (trans->action == MemAction_Write) {
    if (trans->action == MemAction_Write) {
        for (uint64_t i = 0; i < trans->xsize/4; i++) {
        for (uint64_t i = 0; i < trans->xsize/4; i++) {
Line 61... Line 56...
            default:
            default:
                trans->rpayload.b32[i] = ~0;
                trans->rpayload.b32[i] = ~0;
            }
            }
        }
        }
    }
    }
 
    return TRANS_OK;
}
}
 
 
}  // namespace debugger
}  // namespace debugger
 
 
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