Subversion Repositories robust_axi_fabric

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This code is a generic code written in RobustVerilog. In order to convert it to Verilog a RobustVerilog parser is required.

This code is a generic code written in RobustVerilog. In order to convert it to Verilog a RobustVerilog parser is required.

It is possible to download a free RobustVerilog parser from www.provartec.com/edatools.

It is possible to download a free RobustVerilog parser from www.provartec.com/edatools.

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RobustVerilog generic AXI interconnect fabric

RobustVerilog generic AXI interconnect fabric

In order to create the Verilog design use the run.sh script in the run directory (notice that the run scripts calls the robust binary (RobustVerilog parser)).

In order to create the Verilog design use the run.sh script in the run directory (notice that the run scripts calls the robust binary (RobustVerilog parser)).

The RobustVerilog top source file is ic.v, it calls the top definition file named def_ic.txt.

The RobustVerilog top source file is ic.v, it calls the top definition file named def_ic.txt.

The default definition file def_ic.txt generates a fabric with 3 masters and 6 slaves.

The default definition file def_ic.txt generates a fabric with 3 masters and 6 slaves.

Changing the interconnect parameters should be made only in def_ic.txt in the src/base directory (changing master num, slave num etc.).

Changing the interconnect parameters should be made only in def_ic.txt in the src/base directory (changing master num, slave num etc.).