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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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//////////////////////////////////////////////////////////////////##>
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INCLUDE def_ic_static.txt
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INCLUDE def_ic_static.txt
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SWAP #FFD #1 ##flip-flop delay
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SWAP #FFD #1 ##flip-flop delay
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SWAP PREFIX fabric_MASTER_NUM_SLAVE_NUM ##prefix for all module and file names
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SWAP PREFIX fabric_MASTER_NUM_SLAVE_NUM ##prefix for all module and file names
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SWAP MASTER_NUM 3 ##number of masters
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SWAP MASTER_NUM 3 ##number of masters
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SWAP SLAVE_NUM 6 ##number of slaves
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SWAP SLAVE_NUM 6 ##number of slaves
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DEFINE DEF_DECERR_SLV ##use interanl decode slave error
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DEFINE DEF_DECERR_SLV ##use interanl decode slave error
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SWAP ID_BITS 3 ##AXI ID bits
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SWAP ID_BITS 3 ##AXI ID bits
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LOOP M0_IDX 2 ##number of IDs for master 0
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LOOP M0_IDX 2 ##number of IDs for master 0
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SWAP ID_M0_ID0 ID_BITS'b000 ##master 0 ID0
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SWAP ID_M0_ID0 ID_BITS'b000 ##master 0 ID0
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SWAP ID_M0_ID1 ID_BITS'b001 ##master 0 ID1
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SWAP ID_M0_ID1 ID_BITS'b001 ##master 0 ID1
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LOOP M1_IDX 1 ##number of IDs for master 1
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LOOP M1_IDX 1 ##number of IDs for master 1
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SWAP ID_M1_ID0 ID_BITS'b011 ##master 1 ID0
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SWAP ID_M1_ID0 ID_BITS'b011 ##master 1 ID0
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LOOP M2_IDX 1 ##number of IDs for master 2
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LOOP M2_IDX 1 ##number of IDs for master 2
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SWAP ID_M2_ID0 ID_BITS'b101 ##master 2 ID0
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SWAP ID_M2_ID0 ID_BITS'b101 ##master 2 ID0
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SWAP CMD_DEPTH 8 ##AXI command depth for read and write
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SWAP CMD_DEPTH 8 ##AXI command depth for read and write
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SWAP DATA_BITS 64 ##AXI data bits
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SWAP DATA_BITS 64 ##AXI data bits
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SWAP ADDR_BITS 32 ##AXI address bits
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SWAP ADDR_BITS 32 ##AXI address bits
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SWAP USER_BITS 4 ##AXI user bits
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SWAP USER_BITS 4 ##AXI user bits
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