<##//////////////////////////////////////////////////////////////////
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<##//////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Author: Eyal Hochberg ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// eyal@provartec.com ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////##>
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//////////////////////////////////////////////////////////////////##>
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OUTFILE PREFIX_ic_MSTR_SLV_arbiter.v
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OUTFILE PREFIX_ic_MSTR_SLV_arbiter.v
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ITER MX MSTRNUM
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ITER MX MSTRNUM
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ITER SX SLVNUM
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ITER SX SLVNUM
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module PREFIX_ic_MSTR_SLV_arbiter(PORTS);
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module PREFIX_ic_MSTR_SLV_arbiter(PORTS);
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input clk;
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input clk;
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input reset;
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input reset;
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input [MSTRNUM-1:0] M_last;
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input [MSTRNUM-1:0] M_last;
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input [MSTRNUM-1:0] M_req;
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input [MSTRNUM-1:0] M_req;
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input [MSTRNUM-1:0] M_grant;
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input [MSTRNUM-1:0] M_grant;
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input [LOG2(SLVNUM)-1:0] MMX_slave;
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input [LOG2(SLVNUM)-1:0] MMX_slave;
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output [MSTRNUM-1:0] SSX_master;
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output [MSTRNUM-1:0] SSX_master;
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reg [MSTRNUM:0] SSX_master_prio_reg;
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reg [MSTRNUM:0] SSX_master_prio_reg;
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wire [MSTRNUM-1:0] SSX_master_prio;
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wire [MSTRNUM-1:0] SSX_master_prio;
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reg [MSTRNUM-1:0] SSX_master_d;
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reg [MSTRNUM-1:0] SSX_master_d;
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wire [MSTRNUM-1:0] M_SSX;
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wire [MSTRNUM-1:0] M_SSX;
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wire [MSTRNUM-1:0] M_SSX_valid;
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wire [MSTRNUM-1:0] M_SSX_valid;
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wire [MSTRNUM-1:0] M_SSX_prio;
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wire [MSTRNUM-1:0] M_SSX_prio;
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reg [MSTRNUM-1:0] M_SSX_burst;
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reg [MSTRNUM-1:0] M_SSX_burst;
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parameter MASTER_NONE = BIN(0 MSTRNUM);
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parameter MASTER_NONE = BIN(0 MSTRNUM);
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parameter MASTERMX = BIN(EXPR(2^MX) MSTRNUM);
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parameter MASTERMX = BIN(EXPR(2^MX) MSTRNUM);
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IFDEF DEF_PRIO
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IFDEF DEF_PRIO
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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begin
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begin
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SSX_master_prio_reg[MSTRNUM:1] <= #FFD {MSTRNUM{1'b0}};
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SSX_master_prio_reg[MSTRNUM:1] <= #FFD {MSTRNUM{1'b0}};
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SSX_master_prio_reg[0] <= #FFD 1'b1;
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SSX_master_prio_reg[0] <= #FFD 1'b1;
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end
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end
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else if (|(M_req & M_grant & M_last))
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else if (|(M_req & M_grant & M_last))
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begin
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begin
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SSX_master_prio_reg[MSTRNUM:1] <= #FFD SSX_master_prio_reg[MSTRNUM-1:0];
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SSX_master_prio_reg[MSTRNUM:1] <= #FFD SSX_master_prio_reg[MSTRNUM-1:0];
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SSX_master_prio_reg[0] <= #FFD SSX_master_prio_reg[MSTRNUM-1];
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SSX_master_prio_reg[0] <= #FFD SSX_master_prio_reg[MSTRNUM-1];
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end
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end
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assign SSX_master_prio = SSX_master_prio_reg[MSTRNUM-1:0];
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assign SSX_master_prio = SSX_master_prio_reg[MSTRNUM-1:0];
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assign M_SSX_prio = M_SSX_valid & SSX_master_prio;
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assign M_SSX_prio = M_SSX_valid & SSX_master_prio;
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ENDIF DEF_PRIO
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ENDIF DEF_PRIO
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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begin
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begin
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SSX_master_d <= #FFD {MSTRNUM{1'b0}};
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SSX_master_d <= #FFD {MSTRNUM{1'b0}};
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end
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end
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else
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else
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begin
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begin
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SSX_master_d <= #FFD SSX_master;
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SSX_master_d <= #FFD SSX_master;
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end
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end
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LOOP MX MSTRNUM
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LOOP MX MSTRNUM
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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begin
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begin
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M_SSX_burst[MX] <= #FFD 1'b0;
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M_SSX_burst[MX] <= #FFD 1'b0;
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end
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end
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else if (M_req[MX])
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else if (M_req[MX])
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begin
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begin
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M_SSX_burst[MX] <= #FFD SSX_master[MX] & (M_grant[MX] ? (~M_last[MX]) : 1'b1);
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M_SSX_burst[MX] <= #FFD SSX_master[MX] & (M_grant[MX] ? (~M_last[MX]) : 1'b1);
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end
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end
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ENDLOOP MX
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ENDLOOP MX
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assign M_SSX = {CONCAT(MMX_slave == 'dSX ,)};
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assign M_SSX = {CONCAT(MMX_slave == 'dSX ,)};
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assign M_SSX_valid = M_SSX & M_req;
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assign M_SSX_valid = M_SSX & M_req;
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LOOP SX SLVNUM
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LOOP SX SLVNUM
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assign SSX_master =
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assign SSX_master =
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M_SSX_burst[MX] ? SSX_master_d :
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M_SSX_burst[MX] ? SSX_master_d :
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IF DEF_PRIO M_SSX_prio[MX] ? MASTERMX :
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IF DEF_PRIO M_SSX_prio[MX] ? MASTERMX :
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M_SSX_valid[MX] ? MASTERMX :
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M_SSX_valid[MX] ? MASTERMX :
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MASTER_NONE;
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MASTER_NONE;
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ENDLOOP SX
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ENDLOOP SX
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endmodule
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endmodule
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